Intel® Processor A100 and A110 on 90 nm Process with 512-KB L2 Cache

To view this page ensure that Adobe Flash Player version 9.0.124 or greater is installed.

Please login or register to make a comment!

Document Number: 316908-002 Intel ® Processor A100 and A110 on 90 nm Process with 512-KB L2 Cache Datasheet January 2008 2Datasheet IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked creserved d or cundefined. d Int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel ® Processor A100 and A110 on 90 nm process with 256-KB L2 cache may contain design defects or errors known ... more. less.

as errata which may c ause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family , not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increase s in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/p roducts/ processor_number for details. Intel ® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardwar e and software configurations. Seehttp://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Intel, Pentium, MMX, Intel SpeedStep and the Intel logo are trademarks of Intel Corporation in the U. S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007 - 2008, Intel Corporation. All rights reserved Datasheet3 Contents 1Introduction ..............................................................................................................7 1.1Terminology.......................................................................................................8 1.2References.........................................................................................................9 2Low Power Features ................................................................................................11 2.1Clock Control and Low Power States....................................................................11 2.1.1Normal State.........................................................................................11 2.1.2AutoHALT Power-Down State...................................................................11 2.1.3Stop-Grant State....................................................................................12 2.1.4HALT/Grant Snoop State.........................................................................12 2.1.5Sleep State...........................................................................................12 2.1.6Deep Sleep State...................................................................................13 2.1.7Deeper Sleep State.................................................................................13 2.2Enhanced Intel SpeedStep® Technology..............................................................14 2.3Front Side Bus Low Power Enhancements.............................................................14 2.4Processor Power Status Indicator (PSI#) Signal.....................................................15 3Electrical Specifications ...........................................................................................17 3.1Power and Ground Pins......................................................................................17 3.1.1FSB Clock (BCLK[1:0]) and Processor Clocking...........................................17 3.2Voltage Identification.........................................................................................17 3.3Catastrophic Thermal Protection..........................................................................19 3.4Signal Terminations and Unused Pins...................................................................19 3.5FSB Frequency Select Signals (BSEL[1:0])............................................................19 3.6FSB Signal Groups.............................................................................................19 3.7CMOS Signals...................................................................................................20 3.8Maximum Ratings..............................................................................................21 3.9Processor DC Specifications................................................................................21 4Package Mechanical Specifications and Ball Information .........................................27 4.1Package Information..........................................................................................27 4.2Processor Ballout...............................................................................................29 4.3Alphabetical Signals Reference............................................................................50 5Thermal Specifications and Design Considerations ..................................................59 5.1Thermal Specifications.......................................................................................61 5.1.1Thermal Diode.......................................................................................61 5.1.2Thermal Diode Offset..............................................................................62 5.1.3Intel® Thermal Monitor...........................................................................63 4Datasheet Figures 1Clock Control States.................................................................................................11 2Active V CC and I CC Load Line for Processor...................................................................24 3Deep Sleep V CC and I CC Load Line for Processor...........................................................24 4Micro-FCBGA Package...............................................................................................28 5Processor Ballout (Top View, Left Side)........................................................................30 6Processor Ballout (top view, right side)........................................................................31 Tables 1References...............................................................................................................9 2Voltage Identification Definition..................................................................................18 3FSB Pin Groups........................................................................................................20 4Processor DC Absolute Maximum Ratings.....................................................................21 5Voltage and Current Specifications (3 W processors).....................................................22 6Voltage and Current Specifications (5 W processors).....................................................23 7FSB Differential BCLK Specifications............................................................................25 8AGTL+ Signal Group DC Specifications........................................................................25 9CMOS Signal Group DC Specifications..........................................................................26 10Open Drain Signal Group DC Specifications..................................................................26 11Processor Ballout by Signal Name...............................................................................32 12Processor Ballout by Ball Number...............................................................................41 13Signal Description.....................................................................................................50 14Processor Power Specifications (3 W processors)..........................................................60 15Processor Power Specifications (5 W processors)..........................................................61 16Thermal Diode Interface............................................................................................62 17Thermal Diode Specification.......................................................................................63 Datasheet5 Revision History § § RevisionDescriptionDate 001"Initial releaseApril 2007 002"Added a 5 W TDP version of the Intel ® Processor A110. January 2008 6Datasheet Datasheet7 Introduction 1Introduction The Intel® Processors A100 and A110 are based on 90 nm process technology featuring 512-KB L2 cache and 400-MHz front side bus (FSB). The processor is a derivative core based on the Intel® Pentium® M processor architecture that delivers performance. The The Intel® Processors A100 and A110 are ultra low-power mobile processors. Note: Throughout this document, the Intel Processors A100 and A110 on 90 nm process with 512-KB L2 cache and 400 MHz FSB will be referred to as cprocessor d. This document contains specifications for the Intel Processors A100 and A110. The following list provides some of the key features on this processor: "Supports Intel® Architecture with Dynamic Execution "On-die, primary 32-KB instruction cache and 32-KB write-back data cache "On-die, 512 KB second level cache with Advanced Transfer Cache Architecture "Way set associativity and ECC (Error Correcting Code) support "Data Prefetch Logic "Intel® Streaming SIMD Extensions 2 (Intel® SSE2) "400 MHz, source-synchronous FSB "Advanced power management features including Enhanced Intel SpeedStep® technology "Micro-FCBGA packaging technology "Manufactured on Intel 9s advanced 90 nanometer process technology with copper interconnect. "Support for MMX* technology and Internet Streaming SIMD instructions "The processor 9s data prefetch logic fetches data to the L2 cache before L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance "Micro-FCBGA packaging technology, including lead free SLI (second level interconnect) technology "Execute Disable Bit support for enhanced security (available on processors with CPU Signature = 06D8h and recommended for implementation on Intel® 945GU Express chipset family-based platforms only) The processor is manufactured on Intel 9s advanced 90 nm process technology with copper interconnect. The processor maintains support for MMX technology and Internet Streaming SIMD instructions and full compatibility with IA-32 software. The on-die, 32-KB Level1 instruction and data caches along with the 512-KB L2 cache with advanced transfer cache architecture enable significant performance improvement over existing mobile processors. The processor 9s data prefetch logic fetches data to the L2 cache before L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance. The streaming Intel SSE2 enable break-through levels of performance in multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition. The new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-D geometry techniques, such as ray tracing. Introduction 8Datasheet The processor 9s 400-MHz FSB uses a split-transaction, deferred reply protocol. The 400-MHz FSB uses source-synchronous transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a cdouble-clocked d or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling technology with low power enhancements. The processor features Enhanced Intel SpeedStep technology, which enables real-time dynamic switching between multiple voltage and frequency points. This results in optimal performance without compromising low power. The processor features the Auto Halt, Stop Grant, Deep Sleep, and Deeper Sleep low power states. The processor uses surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. Intel Processors A100 and A110 with CPU Signature = 06D8h will also include the Execute Disable Bit capability. This feature combined with a support operating system allows memory to be marked as executable or non executable. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel® Architecture Software Developer's Manual for more detailed information. Intel will validate this feature only on Intel 945GU Express chipset family based platforms and recommends customers implement BIOS changes related to this feature, only on Intel 945GU Express chipset family based platforms. Note: The term AGTL+ is used to refer to Assisted GTL+ signalling technology on some Intel processors. 1.1Terminology TermDefinition # A c# d symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data ), the c# d symbol implies that the signal is inverted. For example, D[3:0] = cHLHL d refers to a hex 8A 9, and D[3:0]# = cLHLH d also refers to a hex cA d (H= High logic level, L= Low logic level). Front Side Bus (FSB) Refers to the interface between the processor and system core logic (also known as the chipset components). Datasheet9 Introduction 1.2References Material and concepts available in the following documents may be beneficial when reading this document. § § Table 1.References Document DocumentNumber/ Location Intel ® Pentium ® M Processor on 90 nm Process with 2-MB L2 Cache - Specification Update http://www.intel.com/ design/mobile/ specupdt/302209.htm Mobile Intel ® 945 Express Chipset Family Datasheet http://www.intel.com/ design/mobile/ datashts/309219.htm Mobile Intel ® 945 Express Chipset Family Specification Update http://www.intel.com/ design/mobile/ specupdt/309220.htm Intel ® 64 and IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture http://www.intel.com/ products/processor/ manuals/ Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide Introduction 10Datasheet Datasheet11 Low Power Features 2Low Power Features 2.1Clock Control and Low Power States The processor supports the AutoHALT Power-Down, Stop Grant, Sleep, Deep Sleep, and Deeper Sleep states for optimal power management. See Figure1 for a visual representation of the processor low-power states. 2.1.1Normal State This is the normal operating state for the processor. 2.1.2AutoHALT Power-Down State AutoHALT Power-Down is a low-power state entered when the processor executes the HALT instruction. The processor will transition to the Normal state upon the occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt message. RESET# will cause the processor to immediately initialize itself. A system management interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Power-Down state. See the Intel® 64 and IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Power- Down state. When the system de-asserts the STPCLK# interrupt, the processor will return execution to the HALT state. While in AutoHALT Power-Down state, the processor will process bus snoops and interrupts. Figure 1.Clock Control States snoop occurs Stop Grant Normal Sleep HALT/ Grant Snoop Auto Halt Deep Sleep STPCLK# asserted SLP# asserted SLP# deasserted STPCLK# deasserted snoop serviced HLT instruction snoop serviced snoop occurs DPSLP# de-asserted DPSLP# asserted STPCLK# asserted STPCLK# deasserted halt break V0001-04 core voltage raised core voltage lowered Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt Deeper Sleep Low Power Features 12Datasheet 2.1.3Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle. Since the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to V CCP ) for minimum power drawn by the termination resistors in this state. In addition, all other input pins on the FSB should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the de- assertion of the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be de-asserted ten or more bus clocks after the de-assertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the FSB (see Section2.1.3 ). A transition to the Sleep state (see Section2.1.5 ) will occur with the assertion of the SLP# signal. While in the Stop-Grant State, SMI#, INIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the FSB and it will latch interrupts delivered on the FSB. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state. 2.1.4HALT/Grant Snoop State The processor responds to snoop or interrupt transactions on the FSB while in Stop- Grant state or in AutoHALT Power-Down state. During a snoop or interrupt transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant state or AutoHALT Power-Down state, as appropriate. 2.1.5Sleep State A low power state in which the processor maintains its context, maintains the phase- locked loop (PLL), and has stopped all internal clocks. The Sleep state can be entered only from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop Grant state. SLP# assertions while the processor is not in the Stop-Grant state is out of specification and may result in unapproved operation. Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will cause unpredictable behavior. Datasheet13 Low Power Features In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP# and STPCLK# signals should be de-asserted immediately after RESET# is asserted to ensure the processor correctly executes the reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state by asserting the DPSLP# pin (See Section2.1.6 .). While the processor is in the Sleep state, the SLP# pin must be de-asserted if another asynchronous FSB event needs to occur. 2.1.6Deep Sleep State Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on 945GU chipset-based platforms are as follows: "Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The platform clock chip will stop/tristate BCLK within 2 BCLKs ± a few nanoseconds. "Deep Sleep exit - DPSLP# and CPU_STP# are de-asserted simultaneously. The platform clock chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6 BCLK periods later. To re-enter the Sleep state, the DPSLP# pin must be de-asserted. BCLK can be restarted after DPSLP# de-assertion, as described above. A period of 30 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep State. Once in the Sleep state, the SLP# pin must be de-asserted to re- enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions. 2.1.7Deeper Sleep State The Deeper Sleep state is the lowest power state the processor can enter. This state is functionally identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Low Power Features 14Datasheet 2.2Enhanced Intel SpeedStep® Technology The processor features Enhanced Intel SpeedStep technology. Unlike previous implementations of Intel SpeedStep technology, this technology enables the processor to switch between multiple frequency and voltage points instead of two. This will enable superior performance with optimal power savings. Switching between states is software controlled unlike previous implementations where the GHI# pin is used to toggle between two states. Following are the key features of Enhanced Intel SpeedStep technology: "Multiple voltage/frequency operating points provide optimal performance at the lowest power. "Voltage/Frequency selection is software controlled by writing to processor MSR 9s (Model Specific Registers) thus eliminating chipset dependency. 4If the target frequency is higher than the current frequency, V CC is ramped up by placing a new value on the VID pins and the PLL then locks to the new frequency. 4If the target frequency is lower than the current frequency, the PLL locks to the new frequency and the V CC is changed through the VID pin mechanism. 4Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until its completion. "The processor controls voltage ramp rates internally to ensure glitch free transitions. "Low transition latency and large number of transitions possible per second. 4Processor core (including L2 cache) is unavailable for up to 10 ¼ s during the frequency transition 4The bus protocol (BNR# mechanism) is used to block snooping "No bus master arbiter disable required prior to transition and no processor cache flush necessary. "Improved Intel ® Thermal Monitor mode. 4When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency/ voltage specified in a software programmable MSR. 4The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency/voltage point occurs. 4An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management. 2.3Front Side Bus Low Power Enhancements The processor incorporates the following front side bus (processor system bus) low power enhancements: "Dynamic FSB Power Down "BPRI# control for address and control input buffers "Dynamic On Die Termination disabling "Low V CCP (I/O termination voltage) Datasheet15 Low Power Features The processor incorporates the DPWR# signal that controls the data bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. The on-die termination on the processor FSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/O switching power at all times. 2.4Processor Power Status Indicator (PSI#) Signal The processor incorporates the PSI# signal that is asserted when the processor is in a low power (Deep Sleep or Deeper Sleep) state. This signal is asserted upon Deep Sleep entry and de-asserted upon exit. PSI# can be used to improve the light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. PSI# can also be used to simplify voltage regulator designs since it removes the need for integrated 100 ¼ s timers required to mask the PWRGOOD signal during Deeper Sleep transitions. It also helps loosen PWRGOOD monitoring requirements in the Deeper Sleep state. § § Low Power Features 16Datasheet Datasheet17 Electrical Specifications 3Electrical Specifications 3.1Power and Ground Pins For clean, on-chip power distribution, the processor has a large number of VCC (power) and VSS (ground) inputs. All power pins must be connected to V CC power planes while all VSS pins must be connected to system ground planes. Use of multiple power and ground planes is recommended to reduce I*R drop. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins. 3.1.1FSB Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the processor. As in previous generation processors, the Intel Processor A100 and A110 core frequency is a multiple of the BCLK[1:0] frequency. The processor uses a differential clocking implementation. 3.2Voltage Identification The processor uses six voltage identification pins, VID[5:0], to support automatic selection of power supply voltages. The VID pins for the processor are CMOS outputs driven by the processor VID circuitry. Table2 specifies the voltage level corresponding to the state of VID[5:0]. A c1 d in this refers to a high-voltage level and a c0 d refers to low-voltage level. Electrical Specifications 18Datasheet Table 2.Voltage Identification Definition VID V CC (V) VID V CC (V) 543210543210 0010001.5801001001.132 0010011.5641001011.116 0010101.5481001101.100 0010111.5321001111.084 0011001.5161010001.068 0011011.5001010011.052 0011101.4841010101.036 0011111.4681010111.020 0100001.4521011001.004 0100011.4361011010.988 0100101.4201011100.972 0100111.4041011110.956 0101001.3881100000.940 0101011.3721100010.924 0101101.3561100100.908 0101111.3401100110.892 0110001.3241101000.876 0110011.3081101010.860 0110101.2921101100.844 0110111.2761101110.828 0111001.2601110000.812 0111011.2441110010.796 0111101.2281110100.780 0111111.2121110110.764 1000001.1961111000.748 1000011.1801111010.732 1000101.1641111100.716 1000111.1481111110.700 Datasheet19 Electrical Specifications 3.3Catastrophic Thermal Protection The processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, which halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125°C (maximum), or if the THERMTRIP# signal is asserted, the V CC supply to the processor must be turned off within 500ms to prevent permanent silicon damage due to thermal runaway. 3.4Signal Terminations and Unused Pins All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to V CC , V SS , or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section4.2 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (V SS ). Unused outputs can be left unconnected. For details on signal terminations, contact your Intel Field representative. The TEST1 and TEST2 pins must have a stuffing option connection to V SS separately via 1-k ©, pull-down resistors. 3.5FSB Frequency Select Signals (BSEL[1:0]) These signals are used to select the FSB clock frequency. They should be connected between the processor and the chipset (G)MCH and clock generator on Intel 945GU Express chipset family based platforms. 3.6FSB Signal Groups To simplify the following discussion, the FSB signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependant upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table3 identifies which signals are common clock, source synchronous, and asynchronous. Electrical Specifications 20Datasheet NOTES: 1.Refer to Chapter4 for signal descriptions and termination requirements. 2.BPM[2:0}# and PRDY# are AGTL+ output only signals. 3.In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. 3.7CMOS Signals CMOS input signals are shown in Table3 . Legacy output FERR#, IERR# and other non- AGTL+ signals (THERMTRIP# and PROCHOT#) use Open Drain output buffers. These signals do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the CMOS signals are required to be asserted for at least three BCLKs in order for the processor to recognize them. See Section3.9 for the DC specifications for the CMOS signal groups. Table 3.FSB Pin Groups Signal GroupTypeSignals 1 AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#, TRDY# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, BNR#, BPM[3:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK#, PRDY# AGTL+ Source Synchronous I/O Synchronous to assoc. strobe AGTL+ Strobes Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# CMOS InputAsynchronous A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK# Open Drain OutputAsynchronousFERR#, IERR#, PROCHOT#, THERMTRIP# CMOS OutputAsynchronousPSI#, VID[5:0], BSEL[1:0] CMOS Input Synchronous to TCK TCK, TDI, TMS, TRST# Open Drain Output Synchronous to TCK TDO FSB ClockClockBCLK[1:0], ITP_CLK[1:0] 2 Power/Other COMP[3:0], DBR# 2 , GTLREF, RSVD, TEST2, TEST1, THERMDA, THERMDC, VCC, VCCA[3:0], VCCP, VCCQ[1:0], VCC_SENSE, VSS, VSS_SENSE SignalsAssociated Strobe REQ[4:0]#, A[16:3]#ADSTB[0]# A[31:17]#ADSTB[1]# D[15:0]#, DINV0#DSTBP0#, DSTBN0# D[31:16]#, DINV1#DSTBP1#, DSTBN1# D[47:32]#, DINV2#DSTBP2#, DSTBN2# D[63:48]#, DINV3#DSTBP3#, DSTBN3# Datasheet21 Electrical Specifications 3.8Maximum Ratings Table4 lists the processor 9s maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains protective circuitry to resist damage from electro static discharge (ESD), one should always take precautions to avoid high static voltages or electric fields. NOTES: 1.This rating applies to any processor pin. 2.Contact Intel for storage requirements in excess of one year. 3.9Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table4.3 for the pin signal definitions and signal pin assignments. The DC specifications for these signals are listed in Table9 and Table10 . Table5 through Table10 list the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency mode (HFM) and Lowest Frequency mode (LFM) refer to the highest and lowest core operating frequencies supported on the processor. Active mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states. V CC,BOOT is the default voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the processor are at Tjunction = 100°C. Care should be taken to read all notes associated with each parameter. Table 4.Processor DC Absolute Maximum Ratings SymbolParameterMinMax UnitNotes T STORAGE Processor storage temperature -40 85°C2 V CC Any processor supply voltage with respect to V SS -0.31.6V1 V inAGTL+ AGTL+ buffer DC input voltage with respect to V SS -0.11.6V1, 2 V inAsynch_CMOS CMOS buffer DC input voltage with respect to V SS -0.11.6V1, 2 Electrical Specifications 22Datasheet NOTES: 1.The voltage specifications are assumed to be measured at a via on the motherboard 9s opposite side of the processor 9s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MOhms minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 2.Specified at V CC,STATIC (nominal) under maximum signal loading conditions. 3.Specified at the VID voltage. 4.Based on simulations and averaged over the duration of any change in current. Specified by design/characterization at nominal V CC . Not 100% tested. 5.Measured at the bulk capacitors on the motherboard. 6.Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel ® Thermal Monitor 2, Enhanced Intel ® SpeedStep Technology, or Enhanced Halt state). Table 5.Voltage and Current Specifications (3 W processors) SymbolParameter MinTypMaxUnitNotes V CCHFM V CC at Highest Frequency Mode (HFM) 0.796 40.94V6 V CCLFM V CC at Lowest Frequency Mode (LFM) 0.796 40.94V6 V CC,BOOT Default V CC Voltage for Initial Power up 1.14 1.21.26V 1 V CCP AGTL+ Termination Voltage 0.9971.051.102V 1 V CCA PLL Supply Voltage 1.4251.51.575V 1 V CCDPRSLP,TR Transient Deeper Sleep Voltage 0.6690.7260.783V 1 V CCDPRSLP,ST Static Deeper Sleep Voltage 0.6790.7260.773V 1 I CC 600MHz & LFM V CC 4 44.5A 2 800 MHz & HFM V CC 4 44.8A I AH , I SGNT I CC Auto-Halt & Stop-Grant HFM LFM 4 42.7 2.5 A 3 I SLP I CC Sleep HFM LFM 4 42.5 2.4 A 3 I DSLP I CC Deep Sleep HFM LFM 4 42.4 2.3 A 3 I DPRSLP I CC Deeper Sleep (C4) 0.7 V 4 42.0A 3 dI CC/DT V CC Power Supply Current Slew Rate 4 40.5A/ns 4, 5 I CCA I CC for V CCA Supply 4 4120mA I CCP I CC for V CCP Supply 4 42.5A Datasheet23 Electrical Specifications NOTES: 1.The voltage specifications are assumed to be measured at a via on the motherboard 9s opposite side of the processor 9s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MOhms minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 2.Specified at V CC,STATIC (nominal) under maximum signal loading conditions. 3.Specified at the VID voltage. 4.Based on simulations and averaged over the duration of any change in current. Specified by design/characterization at nominal V CC . Not 100% tested. 5.Measured at the bulk capacitors on the motherboard. 6.Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Intel Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Enhanced Halt state). Table 6.Voltage and Current Specifications (5 W processors) Symbol Parameter Min Typ Max UnitNotes V CCHFM V CC at Highest Frequency Mode (HFM) 0.828 41.052V6 V CCLFM V CC at Lowest Frequency Mode (LFM) 0.828 41.052V6 V CC,BOOT Default V CC Voltage for Initial Power up 1.14 1.21.26V 1 V CCP AGTL+ Termination Voltage 0.9971.051.102V 1 V CCA PLL Supply Voltage 1.4251.51.575V 1 V CCDPRSLP,TR Transient Deeper Sleep Voltage 0.6690.7260.783V 1 V CCDPRSLP,ST Static Deeper Sleep Voltage 0.6790.7260.773V 1 I CC 600MHz & LFM V CC 4 46.8A 2 800 MHz & HFM V CC 4 47.6A I AH , I SGNT I CC Auto-Halt & Stop-Grant HFM LFM 4 45.3 4.9 A 3 I SLP I CC Sleep HFM LFM 4 45.2 4.8 A 3 I DSLP I CC Deep Sleep HFM LFM 4 44.9 4.6 A 3 I DPRSLP I CC Deeper Sleep (C4) 0.7 V 4 43.9A 3 dI CC/DT V CC Power Supply Current Slew Rate 4 40.5A/ns 4, 5 I CCA I CC for V CCA Supply 4 4120mA I CCP I CC for V CCP Supply 4 42.5A Electrical Specifications 24Datasheet Figure 2.Active V CC and I CC Load Line for Processor Figure 3.Deep Sleep V CC and I CC Load Line for Processor I CC-CORE max {HFM|LFM} V CC-CORE [V] +/-1.5% from Nominal =VR Error V CC-CORE, DC min {HFM|LFM} V CC-CORE, DC max {HFM|LFM} V CC-CORE max {HFM|LFM} V CC-CORE min {HFM|LFM} 10mV= RIPPLE 0 Slope = -4.5mV/A at package V CC-CORE nom {HFM|LFM} I CC-CORE max {HFM|LFM} V CC-CORE [V] +/-1.5% from Nominal =VR Error V CC-CORE, DC min {HFM|LFM} V CC-CORE, DC max {HFM|LFM} V CC-CORE max {HFM|LFM} V CC-CORE min {HFM|LFM} 10mV= RIPPLE 0 Slope = -4.5mV/A at package V CC-CORE nom {HFM|LFM} 31.2% Datasheet25 Electrical Specifications NOTES: 1.Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3.Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver switches. It includes input threshold hysteresis. 4.For Vin between 0 V and V H . 5.Cpad includes die capacitance only. No package parasitics are included. 6.V CROSS is defined as the total variation of all crossing voltages as defined in note 2. NOTES: 1.Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.V IL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3.V IH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4.V IH and V OH may experience excursions above V CCP . 5.This is the pull down driver resistance. Measured at 0.31*V CCP . R ON (min) = 0.38*R TT, R ON (typ) = 0.45*R TT, R ON (max) = 0.52*R TT. 6.GTLREF should be generated from V CCP with a 1% tolerance resistor divider. The V CCP referred to in these specifications is the instantaneous V CCP . 7.R TT is the on-die termination resistance measured at V OL of the AGTL+ output driver. Measured at 0.31*V CCP . R TT is connected to VCCP on die. 8.Specified with on die R TT and R ON are turned off. 9.Cpad includes die capacitance only. No package parasitics are included. Table 7.FSB Differential BCLK Specifications SymbolParameterMinTypMaxUnitNotes 1 V L Input Low Voltage 40 4V V H Input High Voltage0.6600.7100.850V V CROSS Crossing Voltage0.250.350.55V2 ? V CROSS Range of Crossing Points N/AN/A0.140V6 V TH Threshold RegionV CROSS 30.100 4V CROSS +0.100V3 I LI Input Leakage Current 4 4± 100µA4 CpadPad Capacitance1.82.32.75pF5 Table 8.AGTL+ Signal Group DC Specifications SymbolParameterMinTypMaxUnitNotes 1 V CCP I/O Voltage0.9971.051.102V GTLREFReference Voltage2/3 V CCP 3 2%2/3 V CCP 2/3 V CCP + 2%V6 V IH Input High VoltageGTLREF+0.1V CCP +0.1V3,6 V IL Input Low Voltage-0.1GTLREF 30.1V2,4 V OH Output High Voltage 4V CCP 4V6 R TT Termination Resistance 475563 © 7 R ON Buffer On Resistance 17.724.7 32.9 © 5 I LI Input Leakage Current 4 4± 100µA8 CpadPad Capacitance1.82.32.75pF9 Electrical Specifications 26Datasheet NOTES: 1.Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.The V CCP referred to in these specifications refers to instantaneous V CCP . 3.Measured at 0.1*V CCP . 4.Measured at 0.9*V CCP . 5.For Vin between 0 V and V CCP . Measured when the driver is tristated. 6.Cpad includes die capacitance only. No package parasitics are included 1.Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.Measured at 0.2 V. 3.V OH is determined by value of the external pull-up resistor to V CCP . 4.For Vin between 0 V and V OH . 5.Cpad includes die capacitance only. No package parasitics are included. § §§ Table 9.CMOS Signal Group DC Specifications SymbolParameterMinTypMaxUnitNotes 1 VCCPI/O Voltage0.9971.051.102V V IL Input Low Voltage CMOS -0.1 40.3*V CCP V2 V IH Input High Voltage0.7*V CCP 4VCCP+0.1V2 V OL Output Low Voltage-0.100.1*V CCP V2 V OH Output High Voltage0.9*V CCP V CCP V CCP +0.1V2 I OL Output Low Current1.49 44.08mA3 I OH Output High Current1.49 44.08mA4 I LI Leakage Current 4 4± 100µA5 CpadPad Capacitance1.02.33.0pF6 Table 10.Open Drain Signal Group DC Specifications SymbolParameterMinTypMaxUnitNotes 1 V OH Output High Voltage 4V CCP 4V3 V OL Output Low Voltage0 40.20V I OL Output Low Current16 450mA2 I LO Leakage Current 4 4± 200µA4 CpadPad Capacitance1.72.33.0pF5 Datasheet27 Package Mechanical Specifications and Ball Information 4Package Mechanical Specifications and Ball Information This chapter contains package mechanical specifications, ballout listing, and signal descriptions. 4.1Package Information The processor is available in a 663-ball, Micro-FCBGA package. The Micro-FCBGA package may have capacitors placed in the area surrounding the die. Because the die- side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. Doing so may short the capacitors, and possibly damage the device or render it inactive. The use of an insulating material between the capacitors and any thermal solution should be considered to prevent capacitor shorting. The mechanical drawing of the Micro-FCBGA package is shown in Figure4 . Package Mechanical Specifications and Ball Information 28Datasheet Figure 4.Micro-FCBGA Package Datasheet29 Package Mechanical Specifications and Ball Information 4.2Processor Ballout Figure5 and Figure6 show the ballout from a top view of the package. Table11 lists the processor ballout by signal name. Table12 lists the processor ballout by ball number. Package Mechanical Specifications and Ball Information 30Datasheet Figure 5.Processor Ballout (Top View, Left Side) 123456789101112131415 A VSSSMI#SLP#DPSLP#BPM1#RSVDTCK A B VSSVSSSTPCLK#IERR#BPM0#RSVDTDI B C VSS VCCS ENSE VSSVSSVSSVSSVSSVSS C D TEST1VSSSENSERSVDINIT#IGNNE#BPM2#RESET# D E NMIVSSVSSRSVDA20M#RSVDBPM3#TMS E F RSVDFERR#PWRGOODVSSVSSVSSVSS F G RSVDVSSVSSVSSVCCPVCCPVCCPVCCP G H RSVDRSVDINTRVCCPVSSVSSVSS H J RSVDVSSVSSVSSVCCPVCCVCCVCC J K RSVDRSVDRSVDVCCPVSSVSSVSS K L LOCK#VSSVSSVSSVCCPVCCVCCVCC L M BPRI#RS0#RSVDVCCPVSSVSSVSS M N RS1#VSSVSSVSSVCCPVCCVCCVCC N P RS2#HIT#VCCPVCCPVSSVSSVSS P R HITM#VSSVSSVSSVCCPVCCVCCVCC R T DRDY#BNR#DBSY#VCCPVSSVSSVSS T U DEFER # VSSVSSVSSVCCPVCCVCCVCC U V TRDY#BR0#RSVDVCCPVSSVSSVSS V W ADS#VSSVSSVSSVCCPVCCVCCVCC W Y REQ3#A6#RSVDVCCPVSSVSSVSS Y AA REQ1#VSSVSSVSSVCCPVCCVCCVCC AA AB A3#A9#A5#VCCPVSSVSSVSS AB AC REQ0#VSSVSSVSSVCCPVCCVCCVCC AC AD REQ4#A4#VCCQ1VCCPVSSVSSVSS AD AE REQ2#VSSVSSVSSVCCPVCCVCCVCC AE AF ADSTB0#A14#COMP2VCCPVSSVSSVSS AF AG A13#VSSVSSVSSVCCPVCCVCCVCC AG AH A10#A11#RSVDVCCPVSSVSSVSS AH AJ A7#VSSVSSVSSVCCPVCCVCCVCC AJ AK A8#A15#RSVDVCCPVSSVSSVSS AK AL A12#VSSVSSVSSVCCPVCCVCCVCC AL AM A16#COMP3A24#RSVDVSSVSSVSS AM AN A30#VSSVSSVSSVCCVCCVCCVCC AN AP A23#A27#A18#RSVDVSSVSSVSS AP AR A20#VSSVSSVSSVCCVCCVCCVCC AR AT ADSTB1#A31#A25#RSVDVSSVSSVSS AT AU A21#VSSVSSVSSVCCVCCVCCVCC AU AV A26#A28#A19#RSVDVSSVSSVSS AV AW A22#VSSVSSVSSVCCVCCVCCVCC AW AY A29#A17#VID1PSI#VSSVSSVSS AY BA VSSVID4VSSVSSVCCVCCVCCVCC BA BB VSSVID5VID2RSVDVSSVSSVSS BB BC VSSVID3VID0VCCVCCVCCVCC BC 123456789101112131415 Datasheet31 Package Mechanical Specifications and Ball Information Figure 6.Processor Ballout (top view, right side) 16171819202122232425262728293031 A BSEL1BCLK0THERMDAD2#DSTBN0#D15#VSS A B RSVDBCLK1THERMDCD8#DSTBP0#D9#D12#VSS B C VSSVSSVSSVSSVSSVSSVSSVSS C D TDOBSEL0 THERMTR IP# D0#D6#D4#RSVDD10# D E TRST# PROCH OT# DPWR#D7#D3#RSVDVSSDINV0# E F VSSVSSVSSVSSVSSVSSD5#D14# F G VCCPVCCPVCCPVCCPVCCPD13#VSSD11# G H VSSVSSVSSVSSVSSVSSD1#D21# H J VCCVCCVCCVCCVCCPRSVDVSSD17# J K VSSVSSVSSVSSVSSVSSRSVDD22# K L VCCVCCVCCVCCVCCPTEST2VSSD16# L M VSSVSSVSSVSSVSSVSSVSSD20# M N VCCVCCVCCVCCVCCPVCCAVSSD25# N P VSSVSSVSSVSSVSSVSSD29#DSTBN1# P R VCCVCCVCCVCCVCCPD23#VSSDSTBP1# R T VSSVSSVSSVSSVSSVSSD18#DINV1# T U VCCVCCVCCVCCVCCPD31#VSSD19# U V VSSVSSVSSVSSVSSVSSD26#D24# V W VCCVCCVCCVCCVCCPD28#VSSD30# W Y VSSVSSVSSVSSVSSVSSCOMP0D27# Y AA VCCVCCVCCVCCVCCPVCCQ0VSSD38# AA AB VSSVSSVSSVSSVSSVSSCOMP1D41# AB AC VCCVCCVCCVCCVCCPD34#VSSD37# AC AD VSSVSSVSSVSSVSSVSSD43#D39# AD AE VCCVCCVCCVCCVCCPD42#VSSDINV2# AE AF VSSVSSVSSVSSVSSVSSD32#D44# AF AG VCCVCCVCCVCCVCCPD33#VSSDSTBN2# AG AH VSSVSSVSSVSSVSSVSSD47#DSTBP2# AH AJ VCCVCCVCCVCCVCCPGTLREFVSSD35# AJ AK VSSVSSVSSVSSVSSVSSD40#D36# AK AL VCCVCCVCCVCCVCCPRSVDVSSD46# AL AM VSSVSSVSSVSSVSSVSSRSVDD45# AM AN VCCVCCVCCVCCVCCPD56#VSSD50# AN AP VSSVSSVSSVSSVSSVSSD52#D48# AP AR VCCVCCVCCVCCVCCPD55#VSSD53# AR AT VSSVSSVSSVSSVSSVSSD54#D57# AT AU VCCVCCVCCVCCVCCD60#VSSD49# AU AV VSSVSSVSSVSSVSSVSSD61#D63# AV AW VCCVCCVCCVCCVCCD59#VSSDSTBP3# AW AY VSSVSSVSSVSSVSSVSSD62#DSTBN3# AY BA VCCVCCVCCVCCVCCD51#VSSVSS BA BB VSSVSSVSSVSSVSSVSS DINV3 # VSS BB BC VCCVCCVCCVCCVCCD58#VSS BC 16171819202122232425262728293031 Package Mechanical Specifications and Ball Information 32Datasheet Table 11.Processor Ballout by Signal Name (Sheet 1 of 18) Signal NameBall # Signal Buffer Type Direction A3#AB2Source SynchInput/Output A4#AD4Source SynchInput/Output A5#AB6Source SynchInput/Output A6#Y4Source SynchInput/Output A7#AJ1Source SynchInput/Output A8#AK2Source SynchInput/Output A9#AB4Source SynchInput/Output A10#AH2Source SynchInput/Output A11#AH4Source SynchInput/Output A12#AL1Source SynchInput/Output A13#AG1Source SynchInput/Output A14#AF4Source SynchInput/Output A15#AK4Source SynchInput/Output A16#AM2Source SynchInput/Output A17#AY4Source SynchInput/Output A18#AP6Source SynchInput/Output A19#AV6Source SynchInput/Output A20#AR1Source SynchInput/Output A21#AU1Source SynchInput/Output A22#AW1Source SynchInput/Output A23#AP2Source SynchInput/Output A24#AM6Source SynchInput/Output A25#AT6Source SynchInput/Output A26#AV2Source SynchInput/Output A27#AP4Source SynchInput/Output A28#AV4Source SynchInput/Output A29#AY2Source SynchInput/Output A30#AN1Source SynchInput/Output A31#AT4Source SynchInput/Output A20M#E9CMOSInput ADS#W1Common ClockInput/Output ADSTB0#AF2Source SynchInput/Output ADSTB1#AT2Source SynchInput/Output BCLK0A19Bus ClockInput BCLK1B18Bus ClockInput BNR#T4Common ClockInput/Output BPM0#B10Common ClockOutput BPM1#A11Common ClockOutput BPM2#D12Common ClockOutput BPM3#E13Common ClockOutput BPRI#M2Common ClockInput BR0#V4Common ClockInput/Output BSEL0D18CMOSOutput BSEL1A17CMOSOutput COMP0Y28Power/OtherInput/Output COMP1AB28Power/OtherInput/Output COMP2AF6Power/OtherInput/Output COMP3AM4Power/OtherInput/Output D0#D22Source SynchInput/Output D1#H28Source SynchInput/Output D2#A23Source SynchInput/Output D3#E25Source SynchInput/Output D4#D26Source SynchInput/Output D5#F28Source SynchInput/Output D6#D24Source SynchInput/Output D7#E23Source SynchInput/Output D8#B22Source SynchInput/Output D9#B26Source SynchInput/Output D10#D30Source SynchInput/Output D11#G31Source SynchInput/Output D12#B28Source SynchInput/Output D13#G27Source SynchInput/Output D14#F30Source SynchInput/Output D15#A27Source SynchInput/Output D16#L31Source SynchInput/Output D17#J31Source SynchInput/Output D18#T28Source SynchInput/Output D19#U31Source SynchInput/Output D20#M30Source SynchInput/Output D21#H30Source SynchInput/Output D22#K30Source SynchInput/Output D23#R27Source SynchInput/Output D24#V30Source SynchInput/Output D25#N31Source SynchInput/Output D26#V28Source SynchInput/Output D27#Y30Source SynchInput/Output Table 11.Processor Ballout by Signal Name (Sheet 2 of 18) Signal NameBall # Signal Buffer Type Direction Package Mechanical Specifications and Ball Information Datasheet33 D28#W27Source SynchInput/Output D29#P28Source SynchInput/Output D30#W31Source SynchInput/Output D31#U27Source SynchInput/Output D32#AF28Source SynchInput/Output D33#AG27Source SynchInput/Output D34#AC27Source SynchInput/Output D35#AJ31Source SynchInput/Output D36#AK30Source SynchInput/Output D37#AC31Source SynchInput/Output D38#AA31Source SynchInput/Output D39#AD30Source SynchInput/Output D40#AK28Source SynchInput/Output D41#AB30Source SynchInput/Output D42#AE27Source SynchInput/Output D43#AD28Source SynchInput/Output D44#AF30Source SynchInput/Output D45#AM30Source SynchInput/Output D46#AL31Source SynchInput/Output D47#AH28Source SynchInput/Output D48#AP30Source SynchInput/Output D49#AU31Source SynchInput/Output D50#AN31Source SynchInput/Output D51#BA27Source SynchInput/Output D52#AP28Source SynchInput/Output D53#AR31Source SynchInput/Output D54#AT28Source SynchInput/Output D55#AR27Source SynchInput/Output D56#AN27Source SynchInput/Output D57#AT30Source SynchInput/Output D58#BC27Source SynchInput/Output D59#AW27Source SynchInput/Output D60#AU27Source SynchInput/Output D61#AV28Source SynchInput/Output D62#AY28Source SynchInput/Output D63#AV30Source SynchInput/Output DBSY#T6Common ClockInput/Output DEFER#U1Common ClockInput Table 11.Processor Ballout by Signal Name (Sheet 3 of 18) Signal NameBall # Signal Buffer Type Direction DINV0#E31Source SynchInput/Output DINV1#T30CMOSInput/Output DINV2#AE31Source SynchInput/Output DINV3#BB28Source SynchInput/Output DPSLP#A9CMOSInput DPWR#E21Common ClockInput DRDY#T2Common ClockInput/Output DSTBN0#A25Source SynchInput/Output DSTBN1#P30Source SynchInput/Output DSTBN2#AG31Source SynchInput/Output DSTBN3#AY30Source SynchInput/Output DSTBP0#B24Source SynchInput/Output DSTBP1#R31Source SynchInput/Output DSTBP2#AH30Source SynchInput/Output DSTBP3#AW31Source SynchInput/Output FERR#F4Open DrainOutput GTLREFAJ27Power/OtherInput HIT#P4Common ClockInput/Output HITM#R1Common ClockInput/Output IERR#B8Open DrainOutput IGNNE#D10CMOSInput INIT#D8CMOSInput INTRH6 LOCK#L1Common ClockInput/Output NMIE1 PROCHOT#E19Open DrainOutput PSI#AY8CMOSOutput PWRGOODF6CMOSInput REQ0#AC1Source SynchInput/Output REQ1#AA1Source SynchInput/Output REQ2#AE1Source SynchInput/Output REQ3#Y2Source SynchInput/Output REQ4#AD2Source SynchInput/Output RESET#D14Common ClockInput RS0#M4Common ClockInput RS1#N1Common ClockInput RS2#P2Common ClockInput RSVDA13Reserved Table 11.Processor Ballout by Signal Name (Sheet 4 of 18) Signal NameBall # Signal Buffer Type Direction Package Mechanical Specifications and Ball Information 34Datasheet RSVDB12Reserved RSVDB16Reserved RSVDD6Reserved RSVDD28Reserved RSVDE7Reserved RSVDE11Reserved RSVDE27Reserved RSVDF2Reserved RSVDG1Reserved RSVDH2Reserved RSVDH4Reserved RSVDJ1Reserved RSVDJ27Reserved RSVDK2Reserved RSVDK4Reserved RSVDK6Reserved RSVDK28Reserved RSVDM6Reserved RSVDV6Reserved RSVDY6Reserved RSVDAH6Reserved RSVDAK6Reserved RSVDAL27Reserved RSVDAM8Reserved RSVDAM28Reserved RSVDAP8Reserved RSVDAT8Reserved RSVDAV8Reserved RSVDBB8Reserved SLP#A7CMOSInput SMI#A5CMOSInput STPCLK#B6CMOSInput TCKA15CMOSInput TDIB14CMOSInput TDOD16Open DrainOutput TEST1D2Test TEST2L27Test THERMDAA21Power/Other Table 11.Processor Ballout by Signal Name (Sheet 5 of 18) Signal NameBall # Signal Buffer Type Direction THERMDCB20Power/Other THERMTRIP#D20Open DrainOutput TMSE15CMOSInput TRDY#V2Common ClockInput TRST#E17CMOSInput VCCJ11Power/Other VCCJ13Power/Other VCCJ15Power/Other VCCJ17Power/Other VCCJ19Power/Other VCCJ21Power/Other VCCJ23Power/Other VCCL11Power/Other VCCL13Power/Other VCCL15Power/Other VCCL17Power/Other VCCL19Power/Other VCCL21Power/Other VCCL23Power/Other VCCN11Power/Other VCCN13Power/Other VCCN15Power/Other VCCN17Power/Other VCCN19Power/Other VCCN21Power/Other VCCN23Power/Other VCCR11Power/Other VCCR13Power/Other VCCR15Power/Other VCCR17Power/Other VCCR19Power/Other VCCR21Power/Other VCCR23Power/Other VCCU11Power/Other VCCU13Power/Other VCCU15Power/Other VCCU17Power/Other VCCU19Power/Other Table 11.Processor Ballout by Signal Name (Sheet 6 of 18) Signal NameBall # Signal Buffer Type Direction Package Mechanical Specifications and Ball Information Datasheet35 VCCU21Power/Other VCCU23Power/Other VCCW11Power/Other VCCW13Power/Other VCCW15Power/Other VCCW17Power/Other VCCW19Power/Other VCCW21Power/Other VCCW23Power/Other VCCAA11Power/Other VCCAA13Power/Other VCCAA15Power/Other VCCAA17Power/Other VCCAA19Power/Other VCCAA21Power/Other VCCAA23Power/Other VCCAC11Power/Other VCCAC13Power/Other VCCAC15Power/Other VCCAC17Power/Other VCCAC19Power/Other VCCAC21Power/Other VCCAC23Power/Other VCCAE11Power/Other VCCAE13Power/Other VCCAE15Power/Other VCCAE17Power/Other VCCAE19Power/Other VCCAE21Power/Other VCCAE23Power/Other VCCAG11Power/Other VCCAG13Power/Other VCCAG15Power/Other VCCAG17Power/Other VCCAG19Power/Other VCCAG21Power/Other VCCAG23Power/Other VCCAJ11Power/Other Table 11.Processor Ballout by Signal Name (Sheet 7 of 18) Signal NameBall # Signal Buffer Type Direction VCCAJ13Power/Other VCCAJ15Power/Other VCCAJ17Power/Other VCCAJ19Power/Other VCCAJ21Power/Other VCCAJ23Power/Other VCCAL11Power/Other VCCAL13Power/Other VCCAL15Power/Other VCCAL17Power/Other VCCAL19Power/Other VCCAL21Power/Other VCCAL23Power/Other VCCAN9Power/Other VCCAN11Power/Other VCCAN13Power/Other VCCAN15Power/Other VCCAN17Power/Other VCCAN19Power/Other VCCAN21Power/Other VCCAN23Power/Other VCCAR9Power/Other VCCAR11Power/Other VCCAR13Power/Other VCCAR15Power/Other VCCAR17Power/Other VCCAR19Power/Other VCCAR21Power/Other VCCAR23Power/Other VCCAU9Power/Other VCCAU11Power/Other VCCAU13Power/Other VCCAU15Power/Other VCCAU17Power/Other VCCAU19Power/Other VCCAU21Power/Other VCCAU23Power/Other VCCAU25Power/Other Table 11.Processor Ballout by Signal Name (Sheet 8 of 18) Signal NameBall # Signal Buffer Type Direction Package Mechanical Specifications and Ball Information 36Datasheet VCCAW9Power/Other VCCAW11Power/Other VCCAW13Power/Other VCCAW15Power/Other VCCAW17Power/Other VCCAW19Power/Other VCCAW21Power/Other VCCAW23Power/Other VCCAW25Power/Other VCCBA9Power/Other VCCBA11Power/Other VCCBA13Power/Other VCCBA15Power/Other VCCBA17Power/Other VCCBA19Power/Other VCCBA21Power/Other VCCBA23Power/Other VCCBA25Power/Other VCCBC9Power/Other VCCBC11Power/Other VCCBC13Power/Other VCCBC15Power/Other VCCBC17Power/Other VCCBC19Power/Other VCCBC21Power/Other VCCBC23Power/Other VCCBC25Power/Other VCCAN27Power/Other VCCPG9Power/Other VCCPG11Power/Other VCCPG13Power/Other VCCPG15Power/Other VCCPG17Power/Other VCCPG19Power/Other VCCPG21Power/Other VCCPG23Power/Other VCCPG25Power/Other VCCPH8Power/Other Table 11.Processor Ballout by Signal Name (Sheet 9 of 18) Signal NameBall # Signal Buffer Type Direction VCCPJ9Power/Other VCCPJ25Power/Other VCCPK8Power/Other VCCPL9Power/Other VCCPL25Power/Other VCCPM8Power/Other VCCPN9Power/Other VCCPN25Power/Other VCCPP6Power/Other VCCPP8Power/Other VCCPR9Power/Other VCCPR25Power/Other VCCPT8Power/Other VCCPU9Power/Other VCCPU25Power/Other VCCPV8Power/Other VCCPW9Power/Other VCCPW25Power/Other VCCPY8Power/Other VCCPAA9Power/Other VCCPAA25Power/Other VCCPAB8Power/Other VCCPAC9Power/Other VCCPAC25Power/Other VCCPAD8Power/Other VCCPAE9Power/Other VCCPAE25Power/Other VCCPAF8Power/Other VCCPAG9Power/Other VCCPAG25Power/Other VCCPAH8Power/Other VCCPAJ9Power/Other VCCPAJ25Power/Other VCCPAK8Power/Other VCCPAL9Power/Other VCCPAL25Power/Other VCCPAN25Power/Other VCCPAR25Power/Other Table 11.Processor Ballout by Signal Name (Sheet 10 of 18) Signal NameBall # Signal Buffer Type Direction Package Mechanical Specifications and Ball Information Datasheet37 VCCQ0AA27Power/Other VCCQ1AD6Power/Other VCCSENSEC3Power/OtherOutput VID0BC7CMOSOutput VID1AY6CMOSOutput VID2BB6CMOSOutput VID3BC5CMOSOutput VID4BA3CMOSOutput VID5BB4CMOSOutput VSSA3Power/Other VSSA29Power/Other VSSB2Power/Other VSSB4Power/Other VSSB30Power/Other VSSC1Power/Other VSSC5Power/Other VSSC7Power/Other VSSC9Power/Other VSSC11Power/Other VSSC13Power/Other VSSC15Power/Other VSSC17Power/Other VSSC19Power/Other VSSC21Power/Other VSSC23Power/Other VSSC25Power/Other VSSC27Power/Other VSSC29Power/Other VSSC31Power/Other VSSE3Power/Other VSSE5Power/Other VSSE29Power/Other VSSF8Power/Other VSSF10Power/Other VSSF12Power/Other VSSF14Power/Other VSSF16Power/Other VSSF18Power/Other Table 11.Processor Ballout by Signal Name (Sheet 11 of 18) Signal NameBall # Signal Buffer Type Direction VSSF20Power/Other VSSF22Power/Other VSSF24Power/Other VSSF26Power/Other VSSG3Power/Other VSSG5Power/Other VSSG7Power/Other VSSG29Power/Other VSSH10Power/Other VSSH12Power/Other VSSH14Power/Other VSSH16Power/Other VSSH18Power/Other VSSH20Power/Other VSSH22Power/Other VSSH24Power/Other VSSH26Power/Other VSSJ3Power/Other VSSJ5Power/Other VSSJ7Power/Other VSSJ29Power/Other VSSK10Power/Other VSSK12Power/Other VSSK14Power/Other VSSK16Power/Other VSSK18Power/Other VSSK20Power/Other VSSK22Power/Other VSSK24Power/Other VSSK26Power/Other VSSL3Power/Other VSSL5Power/Other VSSL7Power/Other VSSL29Power/Other VSSM10Power/Other VSSM12Power/Other VSSM14Power/Other VSSM16Power/Other Table 11.Processor Ballout by Signal Name (Sheet 12 of 18) Signal NameBall # Signal Buffer Type Direction Package Mechanical Specifications and Ball Information 38Datasheet VSSM18Power/Other VSSM20Power/Other VSSM22Power/Other VSSM24Power/Other VSSM26Power/Other VSSM28Power/Other VSSN3Power/Other VSSN5Power/Other VSSN7Power/Other VSSN29Power/Other VSSP10Power/Other VSSP12Power/Other VSSP14Power/Other VSSP16Power/Other VSSP18Power/Other VSSP20Power/Other VSSP22Power/Other VSSP24Power/Other VSSP26Power/Other VSSR3Power/Other VSSR5Power/Other VSSR7Power/Other VSSR29Power/Other VSST10Power/Other VSST12Power/Other VSST14Power/Other VSST16Power/Other VSST18Power/Other VSST20Power/Other VSST22Power/Other VSST24Power/Other VSST26Power/Other VSSU3Power/Other VSSU5Power/Other VSSU7Power/Other VSSU29Power/Other VSSV10Power/Other VSSV12Power/Other Table 11.Processor Ballout by Signal Name (Sheet 13 of 18) Signal NameBall # Signal Buffer Type Direction VSSV14Power/Other VSSV16Power/Other VSSV18Power/Other VSSV20Power/Other VSSV22Power/Other VSSV24Power/Other VSSV26Power/Other VSSW3Power/Other VSSW5Power/Other VSSW7Power/Other VSSW29Power/Other VSSY10Power/Other VSSY12Power/Other VSSY14Power/Other VSSY16Power/Other VSSY18Power/Other VSSY20Power/Other VSSY22Power/Other VSSY24Power/Other VSSY26Power/Other VSSAA3Power/Other VSSAA5Power/Other VSSAA7Power/Other VSSAA29Power/Other VSSAB10Power/Other VSSAB12Power/Other VSSAB14Power/Other VSSAB16Power/Other VSSAB18Power/Other VSSAB20Power/Other VSSAB22Power/Other VSSAB24Power/Other VSSAB26Power/Other VSSAC3Power/Other VSSAC5Power/Other VSSAC7Power/Other VSSAC29Power/Other VSSAD10Power/Other Table 11.Processor Ballout by Signal Name (Sheet 14 of 18) Signal NameBall # Signal Buffer Type Direction Package Mechanical Specifications and Ball Information Datasheet39 VSSAD12Power/Other VSSAD14Power/Other VSSAD16Power/Other VSSAD18Power/Other VSSAD20Power/Other VSSAD22Power/Other VSSAD24Power/Other VSSAD26Power/Other VSSAE3Power/Other VSSAE5Power/Other VSSAE7Power/Other VSSAE29Power/Other VSSAF10Power/Other VSSAF12Power/Other VSSAF14Power/Other VSSAF16Power/Other VSSAF18Power/Other VSSAF20Power/Other VSSAF22Power/Other VSSAF24Power/Other VSSAF26Power/Other VSSAG3Power/Other VSSAG5Power/Other VSSAG7Power/Other VSSAG29Power/Other VSSAH10Power/Other VSSAH12Power/Other VSSAH14Power/Other VSSAH16Power/Other VSSAH18Power/Other VSSAH20Power/Other VSSAH22Power/Other VSSAH24Power/Other VSSAH26Power/Other VSSAJ3Power/Other VSSAJ5Power/Other VSSAJ7Power/Other VSSAJ29Power/Other Table 11.Processor Ballout by Signal Name (Sheet 15 of 18) Signal NameBall # Signal Buffer Type Direction VSSAK10Power/Other VSSAK12Pow

less