Intel® 865G/865GV Chipset Datasheet: Intel® 82865G Graphics and

cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product o rder.<br><br> I 2 C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I 2 C bus/protocol and was developed by Intel. Imple- mentations of the I 2 C bus/protocol may require licenses from various entities, including Philips Electronics N.V.<br><br> and North American Philips Corpor a- tion. Intel, Pentium, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the Unit ed States and other coun- tries. *Other names and brands may be claimed as the property of others.<br><br> Copyright © 2003 32004, Intel Corporation Intel ® 82865G/82865GV GMCH Datasheet 3 Contents 1 Introduction ...........................................................................................................15 1.1 Terminology...................................................................................................16 1.2 Related Documents .......................................................................................17 1.3 Intel ® 865G Chipset System Overview..........................................................18 1.4 Intel ® 82865G GMCH Overview....................................................................20 1.4.1 Host Interface....................................................................................20 1.4.2 System Memory Interface.................................................................20 1.4.3 Hub Interface ....................................................................................21 1.4.4 Communications Streaming Architecture (CSA) Interface................21 1.4.5 Multiplexed AGP and Intel ® DVO Interface.......................................21 1.4.6 Graphics Overview............................................................................22 1.4.7 Display Interface...............................................................................24 1.5 Clock Ratios...................................................................................................24 2 Signal Description ..............................................................................................25 2.1 Host Interface Signals....................................................................................27 2.2 Memory Interface...........................................................................................30 2.2.1 DDR SDRAM Channel A ..................................................................30 2.2.2 DDR SDRAM Channel B ..................................................................31 2.3 Hub Interface .................................................................................................32 2.4 Communication Streaming Architecture (CSA) Interface...............................32 2.5 AGP Interface ................................................................................................33 2.5.1 AGP Addressing Signals...................................................................33 2.5.2 AGP Flow Control Signals ................................................................34 2.5.3 AGP Status Signals ..........................................................................34 2.5.4 AGP Strobes.....................................................................................35 2.5.5 PCI Signals 3AGP Semantics............................................................36 2.5.5.1 PCI Pins during PCI Transactions on AGP Interface ........37 2.5.6 Multiplexed Intel ® DVOs on AGP......................................................37 2.5.7 Intel ® DVO-to-AGP Pin Mapping.......................................................39 2.6 Analog Display Interface................................................................................40 2.7 Clocks, Reset, and Miscellaneous Signals....................................................41 2.8 RCOMP, VREF, VSWING Signals.................................................................42 2.9 Power and Ground Signals............................................................................43 2.10 GMCH Sequencing Requirements.................................................................44 2.11 Signals Used As Straps.................................................................................45 2.11.1 Functional Straps..............................................................................45 2.11.2 Strap Input Signals............................................................................45 2.12 Full and Warm Reset States..........................................................................46 3 Register Description ..........................................................................................47 3.1 Register Terminology.....................................................................................47 3.2 Platform Configuration Structure....................................................................48 3.3 Routing Configuration Accesses....................................................................50 3.3.1 Standard PCI Bus Configuration Mechanism ...................................50 3.3.2 PCI Bus #0 Configuration Mechanism..............................................50 3.3.3 Primary PCI and Downstream Configuration Mechanism.................50 3.3.4 AGP/PCI_B Bus Configuration Mechanism......................................51 4 Intel ® 82865G/82865GV GMCH Datasheet 3.4 I/O Mapped Registers....................................................................................52 3.4.1 CONFIG_ADDRESS 4Configuration Address Register...................53 3.4.2 CONFIG_DATA 4Configuration Data Register................................54 3.5 DRAM Controller/Host-Hub Interface Device Registers (Device 0)...............55 3.5.1 VID 4Vendor Identification Register (Device 0)................................57 3.5.2 DID 4Device Identification Register (Device 0)................................57 3.5.3 PCICMD 4PCI Command Register (Device 0).................................58 3.5.4 PCISTS 4PCI Status Register (Device 0)........................................59 3.5.5 RID 4Revision Identification Register (Device 0).............................60 3.5.6 SUBC 4Sub-Class Code Register (Device 0)..................................60 3.5.7 BCC 4Base Class Code Register (Device 0)...................................60 3.5.8 MLT 4Master Latency Timer Register (Device 0).............................61 3.5.9 HDR 4Header Type Register (Device 0)..........................................61 3.5.10 APBASE 4Aperture Base Configuration Register (Device 0)...........62 3.5.11 SVID 4Subsystem Vendor Identification Register (Device 0)...........63 3.5.12 SID 4Subsystem Identification Register (Device 0)..........................63 3.5.13 CAPPTR 4Capabilities Pointer Register (Device 0).........................63 3.5.14 AGPM 4AGP Miscellaneous Configuration Register (Device 0) .........................................................................................64 3.5.15 GC 4Graphics Control Register (Device 0)......................................65 3.5.16 CSABCONT 4CSA Basic Control Register (Device 0).....................67 3.5.17 FPLLCONT 4 Front Side Bus PLL Clock Control Register (Device 0) .........................................................................................68 3.5.18 PAM[0:6] 4Programmable Attribute Map Registers (Device 0) .........................................................................................69 3.5.19 FDHC 4Fixed Memory(ISA) Hole Control Register (Device 0) .........................................................................................71 3.5.20 SMRAM 4System Management RAM Control Register (Device 0) .........................................................................................72 3.5.21 ESMRAMC 4Extended System Management RAM Control (Device 0) .........................................................................................73 3.5.22 ACAPID 4AGP Capability Identifier Register (Device 0)..................74 3.5.23 AGPSTAT 4AGP Status Register (Device 0)...................................74 3.5.24 AGPCMD 4AGP Command Register (Device 0)..............................76 3.5.25 AGPCTRL 4AGP Control Register (Device 0).................................77 3.5.26 APSIZE 4Aperture Size Register (Device 0)....................................78 3.5.27 ATTBASE 4Aperture Translation Table Register (Device 0)............78 3.5.28 AMTT 4AGP MTT Control Register (Device 0)................................79 3.5.29 LPTT 4AGP Low Priority Transaction Timer Register (Device 0) .........................................................................................80 3.5.30 TOUD 4Top of Used DRAM Register (Device 0).............................81 3.5.31 GMCHCFG 4GMCH Configuration Register (Device 0)...................82 3.5.32 ERRSTS 4Error Status Register (Device 0).....................................84 3.5.33 ERRCMD 4Error Command Register (Device 0).............................85 3.5.34 SKPD 4Scratchpad Data Register (Device 0)..................................86 3.5.35 CAPREG 4Capability Identification Register (Device 0)..................86 3.6 PCI-to-AGP Bridge Configuration Register (Device 1)..................................87 3.6.1 VID1 4Vendor Identification Register (Device 1)..............................88 3.6.2 DID1 4Device Identification Register (Device 1)..............................88 3.6.3 PCICMD1 4PCI Command Register (Device 1)...............................89 3.6.4 PCISTS1 4PCI Status Register (Device 1)......................................90 3.6.5 RID1 4Revision Identification Register (Device 1)...........................91 Intel ® 82865G/82865GV GMCH Datasheet 5 3.6.6 SUBC1 4Sub-Class Code Register (Device 1) ................................91 3.6.7 BCC1 4Base Class Code Register (Device 1).................................91 3.6.8 MLT1 4Master Latency Timer Register (Device 1)...........................92 3.6.9 HDR1 4Header Type Register (Device 1)........................................92 3.6.10 PBUSN1 4Primary Bus Number Register (Device 1).......................92 3.6.11 SBUSN1 4Secondary Bus Number Register (Device 1)..................93 3.6.12 SUBUSN1 4Subordinate Bus Number Register (Device 1).............93 3.6.13 SMLT1 4Secondary Bus Master Latency Timer Register (Device 1)..........................................................................................93 3.6.14 IOBASE1 4I/O Base Address Register (Device 1)...........................94 3.6.15 IOLIMIT1 4I/O Limit Address Register (Device 1)............................94 3.6.16 SSTS1 4Secondary Status Register (Device 1)...............................95 3.6.17 MBASE1 4Memory Base Address Register (Device 1)....................96 3.6.18 MLIMIT1 4Memory Limit Address Register (Device 1).....................97 3.6.19 PMBASE1 4Prefetchable Memory Base Address Register (Device 1)..........................................................................................98 3.6.20 PMLIMIT1 4Prefetchable Memory Limit Address Register (Device 1)..........................................................................................98 3.6.21 BCTRL1 4Bridge Control Register (Device 1)..................................99 3.6.22 ERRCMD1 4Error Command Register (Device 1).........................100 3.7 Integrated Graphics Device Registers (Device 2)........................................101 3.7.1 VID2 4Vendor Identification Register (Device 2)............................102 3.7.2 DID2 4Device Identification Register (Device 2)............................102 3.7.3 PCICMD2 4PCI Command Register (Device 2).............................103 3.7.4 PCISTS2 4PCI Status Register (Device 2) ....................................104 3.7.5 RID2 4Revision Identification Register (Device 2) .........................104 3.7.6 CC 4Class Code Register (Device 2).............................................105 3.7.7 CLS 4Cache Line Size Register (Device 2) ...................................105 3.7.8 MLT2 4Master Latency Timer Register (Device 2).........................105 3.7.9 HDR2 4Header Type Register (Device 2)......................................106 3.7.10 GMADR 4Graphics Memory Range Address Register (Device 2)........................................................................................106 3.7.11 MMADR 4Memory-Mapped Range Address Register (Device 2)........................................................................................107 3.7.12 IOBAR 4I/O Decode Register (Device 2).......................................107 3.7.13 SVID2 4Subsystem Vendor Identification Register (Device 2)........................................................................................108 3.7.14 SID2 4Subsystem Identification Register (Device 2)......................108 3.7.15 ROMADR 4Video BIOS ROM Base Address Registers (Device 2)........................................................................................108 3.7.16 CAPPOINT 4Capabilities Pointer Register (Device 2)...................109 3.7.17 INTRLINE 4Interrupt Line Register (Device 2)...............................109 3.7.18 INTRPIN 4Interrupt Pin Register (Device 2)...................................109 3.7.19 MINGNT 4Minimum Grant Register (Device 2)..............................110 3.7.20 MAXLAT 4Maximum Latency Register (Device 2).........................110 3.7.21 PMCAPID 4Power Management Capabilities Identification Register (Device 2).........................................................................110 3.7.22 PMCAP 4Power Management Capabilities Register (Device 2)........................................................................................111 3.7.23 PMCS 4Power Management Control/Status Register (Device 2)........................................................................................111 3.7.24 SWSMI 4Software SMI Interface Register (Device 2)....................112 6 Intel ® 82865G/82865GV GMCH Datasheet 3.8 PCI-to-CSA Bridge Registers (Device 3).....................................................113 3.8.1 VID3 4Vendor Identification Register (Device 3)............................114 3.8.2 DID3 4Device Identification Register (Device 3)............................114 3.8.3 PCICMD3 4PCI Command Register (Device 3).............................115 3.8.4 PCISTS3 4PCI Status Register (Device 3)....................................116 3.8.5 RID3 4Revision Identification Register (Device 3).........................117 3.8.6 SUBC3 4Class Code Register (Device 3)......................................117 3.8.7 BCC3 4Base Class Code Register (Device 3)...............................117 3.8.8 MLT3 4Master Latency Timer Register (Device 3).........................118 3.8.9 HDR3 4Header Type Register (Device 3)......................................118 3.8.10 PBUSN3 4Primary Bus Number Register (Device 3).....................118 3.8.11 SBUSN3 4Secondary Bus Number Register (Device 3)................119 3.8.12 SMLT3 4Secondary Bus Master Latency Timer Register (Device 3) .......................................................................................119 3.8.13 IOBASE3 4I/O Base Address Register (Device 3).........................120 3.8.14 IOLIMIT3 4I/O Limit Address Register (Device 3)..........................120 3.8.15 SSTS3 4Secondary Status Register (Device 3).............................121 3.8.16 MBASE3 4Memory Base Address Register (Device 3)..................122 3.8.17 MLIMIT3 4Memory Limit Address Register (Device 3)...................123 3.8.18 PMBASE3 4Prefetchable Memory Base Address Register (Device 3) .......................................................................................124 3.8.19 PMLIMIT3 4Prefetchable Memory Limit Address Register (Device 3) .......................................................................................124 3.8.20 BCTRL3 4Bridge Control Register (Device 3)................................125 3.8.21 ERRCMD3 4Error Command Register (Device 3).........................126 3.8.22 CSACNTRL 4CSA Control Register (Device 3).............................126 3.9 Overflow Configuration Registers (Device 6)...............................................127 3.9.1 VID6 4Vendor Identification Register (Device 6)............................127 3.9.2 DID6 4Device Identification Register (Device 6)............................128 3.9.3 PCICMD6 4PCI Command Register (Device 6).............................128 3.9.4 PCISTS6 4PCI Status Register (Device 6)....................................129 3.9.5 RID6 4Revision Identification Register (Device 6).........................129 3.9.6 SUBC6 4Sub-Class Code Register (Device 6)..............................130 3.9.7 BCC6 4Base Class Code Register (Device 6)...............................130 3.9.8 HDR6 4Header Type Register (Device 6)......................................130 3.9.9 BAR6 4Memory Delays Base Address Register (Device 6)...........131 3.9.10 SVID6 4Subsystem Vendor Identification Register (Device 6) .......................................................................................131 3.9.11 SID6 4Subsystem Identification Register (Device 6)......................131 3.10 Device 6 Memory-Mapped I/O Register Space...........................................132 3.10.1 DRB[0:7] 4DRAM Row Boundary Register (Device 6, MMR).............................................................................132 3.10.2 DRA 4DRAM Row Attribute Register (Device 6, MMR).................134 3.10.3 DRT 4DRAM Timing Register (Device 6, MMR)............................135 3.10.4 DRC 4DRAM Controller Mode Register (Device 6, MMR).............136 4 System Address Map ......................................................................................139 4.1 System Memory Address Ranges...............................................................139 4.2 Compatibility Area........................................................................................141 4.3 Extended Memory Area...............................................................................143 4.3.1 15 MB 316 MB Window...................................................................143 4.3.2 Pre-Allocated Memory....................................................................144 Intel ® 82865G/82865GV GMCH Datasheet 7 4.4 AGP Memory Address Ranges....................................................................146 5 Functional Description ...................................................................................147 5.1 Processor Front Side Bus (FSB)..................................................................147 5.1.1 FSB Dynamic Bus Inversion...........................................................147 5.1.2 FSB Interrupt Overview...................................................................148 5.1.2.1 Upstream Interrupt Messages.........................................148 5.2 System Memory Controller ..........................................................................149 5.2.1 DRAM Technologies and Organization...........................................150 5.2.2 Memory Operating Modes ..............................................................150 5.2.2.1 Dynamic Addressing Mode..............................................151 5.2.3 Single-Channel (SC) Mode.............................................................151 5.2.3.1 Linear Mode.....................................................................151 5.2.3.2 Tiled Mode.......................................................................151 5.2.4 Memory Address Translation and Decoding...................................151 5.2.5 Memory Organization and Configuration........................................156 5.2.6 Configuration Mechanism for DIMMS.............................................157 5.2.6.1 Memory Detection and Initialization.................................157 5.2.6.2 SMBus Configuration and Access of the Serial Presence Detect Ports.....................................................................157 5.2.6.3 Memory Register Programming.......................................157 5.2.7 Memory Thermal Management.......................................................158 5.2.7.1 Determining When to Thermal Manage...........................158 5.3 Accelerated Graphics Port (AGP)................................................................158 5.3.1 GMCH AGP Support.......................................................................159 5.3.2 Selecting between AGP 3.0 and AGP 2.0 ......................................159 5.3.3 AGP 3.0 Downshift (4X Data Rate) Mode.......................................159 5.3.3.1 Mechanism for Detecting AGP 2.0, AGP 3.0, or Intel ® DVO.......................................................................160 5.3.4 AGP Target Operations ..................................................................162 5.3.5 AGP Transaction Ordering..............................................................162 5.3.6 Support for PCI-66 Devices............................................................163 5.3.7 8X AGP Protocol.............................................................................163 5.3.7.1 Fast Writes ......................................................................163 5.3.7.2 PCI Semantic Transactions on AGP ...............................163 5.4 Integrated Graphics Controller.....................................................................164 5.4.1 3D Engine.......................................................................................165 5.4.1.1 Setup Engine...................................................................165 5.4.1.2 Scan Converter................................................................166 5.4.1.3 2D Functionality...............................................................166 5.4.1.4 Texture Engine................................................................166 5.4.1.5 Raster Engine..................................................................168 5.4.2 2D Engine.......................................................................................172 5.4.3 Video Engine...................................................................................173 5.4.4 Planes.............................................................................................173 5.4.4.1 Cursor Plane....................................................................173 5.4.4.2 Overlay Plane..................................................................174 5.4.5 Pipes...............................................................................................175 5.5 Display Interfaces ........................................................................................175 5.5.1 Analog Display Port Characteristics................................................176 5.5.2 Digital Display Interface..................................................................177 5.5.2.1 Digital Display Channels 3 Intel ® DVOB and Intel ® DVOC ... 177 8 Intel ® 82865G/82865GV GMCH Datasheet 5.5.3 Synchronous Display......................................................................180 5.6 Power Management.....................................................................................180 5.6.1 Supported ACPI States...................................................................180 5.7 Thermal Management..................................................................................181 5.7.1 External Thermal Sensor Interface Overview.................................181 5.7.1.1 External Thermal Sensor Usage Model ..........................182 5.8 Clocking.......................................................................................................183 6 Electrical Characteristics ..............................................................................185 6.1 Absolute Maximum Ratings.........................................................................185 6.2 Thermal Characteristics...............................................................................185 6.3 Power Characteristics..................................................................................186 6.4 Signal Groups..............................................................................................186 6.5 DC Parameters............................................................................................189 6.6 DAC.............................................................................................................194 6.6.1 DAC DC Characteristics.................................................................194 6.6.2 DAC Reference and Output Specifications.....................................194 6.6.3 DAC AC Characteristics..................................................................195 7 Ballout and Package Information ...............................................................197 7.1 GMCH Ballout..............................................................................................197 7.2 GMCH Package Information........................................................................209 8 Testability ............................................................................................................211 8.1 XOR Test Mode Initialization.......................................................................211 8.2 XOR Chain Definition...................................................................................213 9 Intel ® 82865GV GMCH .....................................................................................221 9.1 No AGP Interface.........................................................................................222 9.2 Intel ® 82865G / 82865GV Signal Differences..............................................222 9.2.1 Functional Straps............................................................................222 9.3 Intel ® 82865G / 82865GV Register Differences...........................................223 9.3.1 DRAM Controller/Host-Hub Interface Device Registers (Device 0) .......................................................................................223 9.3.1.1 Device 0 Registers Not in 82865GV................................223 9.3.1.2 Device 0 Register Bit Differences....................................224 9.3.2 Host-to-AGP Bridge Registers (Device 1).......................................226 9.4 Synchronous Display Differences................................................................226 10 Intel ® 82865GV GMCH Ballout .....................................................................227 11 Intel ® 82865GV GMCH Testability ..............................................................241 11.1 XOR Test Mode Initialization.......................................................................241 11.2 XOR Chain Definition...................................................................................243 Intel ® 82865G/82865GV GMCH Datasheet 9 Figures 1 Intel ® 865G Chipset System Block Diagram..................................................19 2 Intel ® 82865G GMCH Interface Block Diagram.............................................26 3 Intel ® 865G Chipset System Clock and Reset Requirements .......................44 4 Full and Warm Reset Waveforms..................................................................46 5 Conceptual Intel ® 865G Chipset Platform PCI Configuration Diagram .........49 6 Configuration Mechanism Type 0 Configuration Address-to-PCI Address Mapping .................................................................51 7 Configuration Mechanism Type 1 Configuration Address-to-PCI Address Mapping .................................................................52 8 PAM Register Attributes.................................................................................70 9 Memory System Address Map.....................................................................140 10 Detailed Memory System Address Map......................................................140 11 Single-Channel Mode Operation..................................................................149 12 Dual-Channel Mode Operation....................................................................149 13 GMCH Graphics Block Diagram..................................................................164 14 Platform External Sensor.............................................................................182 15 Intel ® 865G Chipset System Clocking Block Diagram.................................183 16 Intel ® 82865G GMCH Ballout Diagram (Top View 4Left Side) ...................198 17 Intel ® 82865G GMCH Ballout Diagram (Top View 4Right Side).................199 18 Intel ® 82865G GMCH Package Dimensions (Top and Side Views)............209 19 Intel ® 82865G GMCH Package Dimensions (Bottom View)........................210 20 XOR Toggling of HCLKP and HCLKN.........................................................211 21 XOR Testing Chains Tested Sequentially....................................................212 22 Intel ® 865GV Chipset System Block Diagram.............................................221 23 Intel ® 82865GV GMCH Ballout Diagram (Top View 4Left Side).................228 24 Intel ® 82865GV GMCH Ballout Diagram (Top View 4Right Side)...............229 25 XOR Toggling of HCLKP and HCLKN.........................................................241 26 XOR Testing Chains Tested Sequentially....................................................242 10 Intel ® 82865G/82865GV GMCH Datasheet Tables 1 General Terminology.....................................................................................16 2 System Memory Clock Ratios........................................................................24 3 Intel ® DVO-to-AGP Pin Mapping...................................................................39 4 Internal GMCH Device Assignment...............................................................49 5 Configuration Address Decoding...................................................................51 6 DRAM Controller/Host-Hub Interface Device Register Address Map (Device 0)................................................................................55 7 PAM Register Attributes ................................................................................70 8 PCI-to-AGP Bridge PCI Configuration Register Address Map (Device 1).....87 9 VGAEN and MDAP Field Definitions.............................................................99 10 Integrated Graphics Device PCI Register Address Map (Device 2)............101 11 PCI-to-CSA Bridge Configuration Register Address Map (Device 3)..........113 12 VGAEN and MDAP Definitions....................................................................125 13 Overflow Device Configuration Register Address Map (Device 6)..............127 14 Device 6 Memory-Mapped I/O Register Address Map................................132 15 Memory Segments and Their Attributes......................................................141 16 Pre-Allocated Memory.................................................................................144 17 System Memory Capacity............................................................................149 18 GMCH Memory Controller Operating Modes...............................................150 19 DRAM Address Translation (Single-Channel Mode) (Non-Dynamic Mode)...................................................................................152 20 DRAM Address Translation (Dual-Channel Mode, Discrete) (Non-Dynamic Mode)...................................................................................152 21 DRAM Address Translation (Dual-Channel Mode, Internal Gfx) (Non-Dynamic Mode)...................................................................................153 22 DRAM Address Translation (Single-Channel Mode) (Dynamic Mode) ..........................................................................................154 23 DRAM Address Translation (Dual-Channel Mode, Discrete) (Dynamic Mode) ..........................................................................................155 24 RAM Address Translation (Dual-Channel Mode, Internal Gfx) (Dynamic Mode) ..........................................................................................156 25 Supported DDR DIMM Configurations.........................................................156 26 Data Bytes on DIMM Used for Programming DRAM Registers...................157 27 AGP Support Matrix.....................................................................................159 28 AGP 3.0 Downshift Mode Parameters.........................................................160 29 Pin and Strap Values Selecting Intel ® DVO, AGP 2.0, and AGP 3.0 ..........161 30 AGP 3.0 Commands Compared to AGP 2.0 ...............................................162 31 Supported Data Rates.................................................................................162 32 Display Port Characteristics.........................................................................176 33 Analog Port Characteristics.........................................................................176 34 Absolute Maximum Ratings.........................................................................185 35 Power Characteristics..................................................................................186 36 Signal Groups..............................................................................................187 37 DC Operating Characteristics......................................................................189 38 DC Characteristics.......................................................................................191 39 DAC DC Characteristics..............................................................................194 40 DAC Reference and Output Specifications..................................................194 41 DAC AC Characteristics ..............................................................................195 42 Intel ® 82865G Ball List by Signal Name ......................................................201 43 XOR Chain Outputs.....................................................................................213 Intel ® 82865G/82865GV GMCH Datasheet 11 44 XOR Chain 0 (60 Inputs) Output Pins: SDM_A0, SDM_B0.........................214 45 XOR Chain 1 (33 Inputs) Output Pins: SDM_A1, SDM_B1.........................215 46 XOR Chain 2 (44 Inputs) Output Pins: SDM_A2, SDM_B2.........................215 47 XOR Chain 3 (41 Inputs) Output Pins: SDM_A3, SDM_B3.........................216 48 XOR Chain 4 (40 Inputs) Output Pins: SDM_A4, SDM_B4.........................216 49 XOR Chain 5 (44 Inputs) Output Pins: SDM_A5, SDM_B5.........................217 50 XOR Chain 6 (40 Inputs) Output Pins: SDM_A6, SDM_B6.........................217 51 XOR Chain 7 (45 Inputs) Output Pins: SDM_A7, SDM_B7.........................218 52 XOR Chain 8 (40 Inputs) Output Pins: SDM_A8, SDM_B8.........................218 53 XOR Chain 9 (62 Inputs) Output Pins: RS2#, DEFER#...............................219 54 XOR Excluded Pins .....................................................................................220 55 Intel ® 82865GV Ball List by Signal Name....................................................231 56 XOR Chain Outputs.....................................................................................243 57 XOR Chain 0 (60 Inputs) Output Pins: SDM_A0, SDM_B0.........................244 58 XOR Chain 1 (33 Inputs) Output Pins: SDM_A1, SDM_B1.........................245 59 XOR Chain 2 (44 Inputs) Output Pins: SDM_A2, SDM_B2.........................245 60 XOR Chain 3 (41 Inputs) Output Pins: SDM_A3, SDM_B3.........................246 61 XOR Chain 4 (40 Inputs) Output Pins: SDM_A4, SDM_B4.........................246 62 XOR Chain 5 (44 Inputs) Output Pins: SDM_A5, SDM_B5.........................247 63 XOR Chain 6 (40 Inputs) Output Pins: SDM_A6, SDM_B6.........................247 64 XOR Chain 7 (45 Inputs) Output Pins: SDM_A7, SDM_B7.........................248 65 XOR Chain 8 (40 Inputs) Output Pins: HTRDY#, BPRI#.............................248 66 XOR Chain 9 (62 Inputs) Output Pins: RS2#, DEFER#...............................249 67 XOR Excluded Pins .....................................................................................250 12 Intel ® 82865G/82865GV GMCH Datasheet Revision History Revision Description Date -001 " Initial Release May 2003 -002 " Corrected A0-A3 ACAPID Register Default Value in Table 6, Section 3.5. June 2003 -003 " Corrected bit A1 in Table 24, RAM Address Translation, 512mb, 64Mx8, from bit 15 to 16.<br><br> June 2003 -004 " Added 82865GV information September 2003 -005 " Replaced Figure 19 in Section 7.2 February 2004 Intel ® 82865G/82865GV GMCH Datasheet 13 Intel ® 82865G GMCH Features I Host Interface Support 4 Intel ® Pentium ® 4 processors with 512-KB L2 cache on 0.13 micron process / Pentium 4 processor on 90 nm process 4 VTT 1.1 V 3 1.55 V ranges 4 64-bit FSB frequencies of 400 MHz (100 MHz bus clock), 533 MHz (133 MHz bus clock), and 800 MHz (200 MHz bus clock). Maximum theoretical BW of 6.4 GB/s. 4 FSB Dynamic Bus Inversion on the data bus 4 32-bit addressing for access to 4 GB of memory space 4 12-deep In Order Queue 4 AGTL+ On-die Termination (ODT) 4 Hyper-Threading Technology I System Memory Controller Support 4 Dual-channel (128 bits wide) DDR memory interface 4 Single-channel (64 bits wide) DDR operation supported 4 Symmetric and asymmetric memory dual-channel upgrade supported 4 128-Mb, 256-Mb, 512-Mb technologies implemented as x8, x16 devices 4 Four bank devices 4 Non-ECC, un-buffered DIMMS only 4 Maximum of two DIMMs per channel, with each DIMM having one or two rows 4 Up to 4 GB system memory 4 Supports up to 16 simultaneously-open pages (four per row) in dual-channel mode and up to 32 open pages in single-channel mode 4 4-KB to 64-KB page sizes (4 KB to 32 KB in single-channel, 8 KB to 64 KB in dual-channel) 4 Supports opportunistic refresh 4 Suspend-to-RAM support using CKE 4 SPD (Serial Presence Detect) Scheme for DIMM Detection supported 4 Supports selective Command-Per-Clock (selective CPC) Accesses 4 DDR (Double Data Rate type 1) Support - Supports maximum of two DDR DIMMs per channel, single-sided and/or double-sided - Supports DDR266, DDR333, DDR400 DIMM modules - Supports DDR channel operation at 266 MHz, 333 MHz and 400 MHz with a Peak BW of 2.1 GB/s, 2.7 GB/s, and 3.2GB/s respectively per channel - Burst length of 4 and 8 for single-channel (32 or 64 bytes per access, respectively); for dual-channel a burst of 4 (64 bytes per access) - Supports SSTL_2 signaling I Communication Streaming Architecture (CSA) Interface 4 Gigabit Ethernet (GbE) communication devices supported on the CSA interface (e.g., Intel ® 82547EI GbE controller) 4 Supports 8-bit Hub Interface 1.5 electrical/transfer protocol 4 266 MB/s point-to-point connection 4 1.5 V operation I Hub Interface (HI) 4 Supports Hub Interface 1.5 electrical/transfer protocol 4 266 MB/s point-to-point connection to the ICH5 4 66 MHz base clock 4 1.5 V operation I AGP Interface Support 4 A single AGP device 4 AGP 3.0 with 4X / 8X AGP data transfers and 4X / 8X fast writes, respectively 4 32-bit 4X/8X data transfers and 4X/8X fast writes 4 Peak BW of 2 GB/s.<br><br> 4 0.8 V and 1.5 V AGP signalling levels; no 3.3 V support 4 AGP 2.0 1X/4X AGP data transfers and 4X fast writes 4 32-deep AGP request queue I Integrated Graphics 4 Core Frequency of 266 MHz 4 VGA/UMA Support 4 High Performance 3D Setup and Render Engine 4 High-Quality/Performance Texture Engine 4 3D Graphics Rendering Enhancements 4 2D Graphics 4 Video DVD/PC-VCR 4 Video Overlay 4 Video Mixer Render Supported (VMR) 4 Bi-Cubic Filter Support I Display Interfaces 4 AGP signals multiplexed with two DVO ports (ADD card supported) 4 Multiplexed Digital Display Channels (Supported with ADD Card) I Analog Display Support 4 350 MHz Integrated 24-bit RAMDAC 4 Up to 2048x1536 @ 75 Hz refresh 4 Hardware Color Cursor 4 DDC2B Compliant Interface 4 Simultaneous Display options with digital display I Digital Display Channels 4 Two channels multiplexed with AGP 4 165 MHz dot clock on each 12-bit interface 4 Can combine two, 12-bit channels to form one, 24-bit interface Supports flat panels up to 2048x1536 @ 60 Hz or digital CRT/HDTV at 1920x1080 @ 85 Hz 4 Supports Hot Plug and Display 4 Supports LVDS, TMDS transmitters or TV-out encoders 4 ADD card utilizes AGP connector 4 Supports one additional flat panel (dCRT) and/or one TV (only when using internal GFX) 4 Three Display Control interfaces (I 2 C/DDC) multiplexed on AGP I GMCH Package 4 37.5 mm x 37.5 mm Flip Chip Ball Grid Array (FC-BGA) package 4 932 solder balls with variable ball pitch 14 Intel ® 82865G/82865GV GMCH Datasheet This page is intentionally left blank. Intel ® 82865G/82865GV GMCH Datasheet 15 Introduction Introduction 1 The Intel ® 82865G and the Intel ® 82865GV chipsets are designed for use in desktop systems based on an Intel ® Pentium ® 4 processor with 512-KB L2 cache on 0.13 micron process in the 478-pin package or the Intel ® Pentium ® 4 processor on 90 nm process, and supports FSB frequencies of 400 MHz, 533 MHz, and 800 MHz. The 82865G GMCH is part of the Intel ® 865G chipset, the 82865GV GMCH is part of the Intel ® 865GV chipset.<br><br> Each chipset contains two main components: Graphics and Memory Controller Hub (GMCH) for the host bridge and I/O Controller Hub for the I/O subsystem. The GMCH provides the processor interface, system memory interface, hub interface, CSA interface and other additional interfaces in an 865G/ 865GV chipset desktop platform. Each GMCH contains an integrated graphics controller (IGD).<br><br> The 865G /865GV chipset use either the 82801EB ICH5 or 82801ER ICH5R for the I/O Controller Hub. This document is the datasheet for the 82865G and the 82865GV Graphics and Memory Controller Hub (GMCH) component. The following are the key feature differences between the 82865G GMCH and 82865GV GMCH: " AGP Interface 4 82865G supports AGP.<br><br> The AGP interface signals are multiplexed with the Intel ® DVO interface signals. The 82865GV does not support AGP. The Intel ® 865G/865GV chipset platform supports the following processors: " Intel ® Pentium ® 4 processor with 512-KB L2 cache on 0.13 micron process in the 478-pin package.<br><br> " Intel ® Pentium ® 4 processor on 90 nm process. Note: Unless otherwise specified, the term processor in this document refers to the Pentium 4 processor with 512-KB L2 cache on 0.13 micron process in the 478-pin package and the Pentium 4 processor on 90 nm process. Note: Unless otherwise specified, the term ICH5 in this document refers to both the 82801EB ICH5 and 82801ER ICH5R.<br><br> Chapter 1 through Chapter 8 describe the 82865G GMCH. The 82865GV GMCH is described in Chapter 9 through Chapter 11 . 16 Intel ® 82865G/82865GV GMCH Datasheet Introduction 1.1 Terminology This section provides the definitions of some of the terms used in this document.<br><br> Table 1. General Terminology (Sheet 1 of 2) Terminology Description AGP Accelerated Graphics Port. In this document AGP refers to the AGP/PCI interface that is in the GMCH.<br><br> The GMCH AGP interface supports only 0.8 V/1.5 V AGP 2.0/AGP 3.0 compliant devices using PCI (66 MHz), AGP 1X (66 MHz), 4X (266 MHz), and 8X (533 MHz) transfers. GMCH does not support any 3.3 V devices. For AGP 2.0, PIPE# and SBA addressing cycles and their associated data phases are generally referred to as AGP transactions.<br><br> FRAME# cycles are generally referred to as AGP/PCI transactions. Bank DRAM chips are divided into multiple banks internally. Commodity parts are all 4 bank, which is the only type the GMCH supports.<br><br> Each bank acts somewhat like a separate DRAM, opening and closing pages independently, allowing different pages to be open in each. Most commands to a DRAM target a specific bank, but some commands (i.e., Precharge All) are targeted at all banks. Multiple banks allows higher performance by interleaving the banks and reducing page miss cycles.<br><br> Channel In the GMCH a DRAM channel is the set of signals that connect to one set of DRAM DIMMs. The GMCH has two DRAM channels, (a pair of DIMMs added at a time, one on each channel). Chipset Core The GMCH internal base logic.<br><br> Column Address The column address selects one DRAM location, or the starting location of a burst, from within the open page on a read or write command. Double-Sided DIMM Terminology often used to describe a DIMM that contains two DRAM rows. Generally, a double-sided DIMM contains two rows, with the exception noted above.<br><br> This terminology is not used in this document. DDR Double Data Rate SDRAM. DDR describes the type of DRAMs that transfer two data items per clock on each pin.<br><br> This is the only type of DRAM supported by the GMCH. Full Reset A Full GMCH Reset is defined in this document when RSTIN# is asserted. GART Graphics Aperture Re-map Table.<br><br> GART is a table in memory containing the page re-map information used during AGP aperture address translations. GMCH Graphics and Memory Controller Hub. The GMCH component contains the processor interface, SDRAM controller, AGP interface, CSA interface and an integrated 3D/2D/display graphics core.<br><br> It communicates with the I/O controller hub (Intel ® ICH5) over a proprietary interconnect called HI. GTLB Graphics Translation Look-aside Buffer. A cache used to store frequently used GART entries.<br><br> Graphics Core The internal graphics related logic in the GMCH. HI Hub Interface. HI is the proprietary hub interface that connects the GMCH to the ICH5.<br><br> In this document HI cycles originating from or destined for the primary PCI interface on the ICH5 are generally referred to as HI/PCI or simply HI cycles. Host This term is used synonymously with processor. Intel ® ICH5 Fifth generation IO Controller Hub component that contains additional functionality compared to the ICH4.<br><br> IGD Integrated Graphics Device. IGD refers to the graphics device integrated into the GMCH. Primary PCI The physical PCI bus that is driven directly by the ICH5 component.<br><br> Communication between PCI and the GMCH occurs over the hub interface. Note that even though the Primary PCI bus is referred to as PCI, it is not PCI Bus 0 from a configuration standpoint. FSB Processor Front-Side Bus.<br><br> This is the processor system bus. Row A group of DRAM chips that fill out the data bus width of the system and are accessed in parallel by each DRAM command. Intel ® 82865G/82865GV GMCH Datasheet 17 Introduction 1.2 Related Documents Row Address The row address is presented to the DRAMs during an Activate command, and indicates which page to open within the specified bank (the bank number is presented also).<br><br> Scalable Bus Processor-to-GMCH interface. The compatible mode of the Scalable Bus is the P6 Bus. The enhanced mode of the Scalable Bus is the P6 Bus plus enhancements primarily consisting of source synchronous transfers for address and data, and FSB interrupt delivery.<br><br> The Intel ® Pentium ® 4 processor implements a subset of the enhanced mode. Single-Sided DIMM Terminology often used to describe a DIMM that contains one DRAM row. Usually one row fits on a single side of the DIMM allowing the backside to be empty.<br><br> SDR Single Data Rate SDRAM. SDRAM Synchronous Dynamic Random Access Memory. Secondary PCI The physical PCI interface that is a subset of the AGP bus driven directly by the GMCH.<br><br> It supports a subset of 32-bit, 66 MHz PCI 2.0 compliant components, but only at 1.5 V (not 3.3 V or 5 V). SSTL_2 Stub Series Terminated Logic for 2.6 Volts (DDR) Document Document Number/ Location Intel ® 865G/865GV/865PE/865P Chipset Platform Design Guide http://developer.intel.com/ design/chipsets/designex/ 252518.htm Intel ® 865G/865GV/865PE/865P Chipset Thermal Design Guide http://developer.intel.com/ design/chipsets/designex/ 252519.htm Intel ® 865G/865GV/865PE/865P Chipset Schematics http://developer.intel.com/ design/chipsets/schematics/ 252813.htm Intel ® 865G/865GV/865PE/865P Chipset CRB Schematics Addendum for the Intel ® Pentium ® 4 processor on 90 nm Process w/Loadline A Platforms - 2 Phase VR http://developer.intel.com/ design/chipsets/schematics/ 300683.htm Intel ® 865G/865GV/865PE/865P Chipset CRB Schematics Addendum for the Intel ® Pentium ® 4 processor on 90 nm Process w/Loadline A Platforms - 3 Phase VR http://developer.intel.com/ design/chipsets/schematics/ 300684.htm Intel ® 82801EB I/O Controller Hub 5 (ICH5) and Intel ® 82801ER I/O Controller Hub 5R (ICH5R) Datasheet http://developer.intel.com/ design/chipsets/specupdt/ 252517.htm Intel ® Pentium ® 4 processor with 512-KB L2 Cache on 0.13 Micron Process Datasheet http://developer.intel.com/ design/pentium4/datashts/ 298643.htm Intel ® Pentium ® 4 processor on 90 nm Process Datasheet http://developer.intel.com/ design/pentium4/datashts/ 300561.htm Intel ® Pentium ® 4 processor on 90 nm Process Thermal and Mechanical Design Guide http://developer.intel.com/ design/Pentium4/guides/ 300564.htm JEDEC Double Data Rate (DDR) SDRAM Specification www.jedec.org Table 1. General Terminology (Sheet 2 of 2) Terminology Description 18 Intel ® 82865G/82865GV GMCH Datasheet Introduction NOTE: For additional related documents, refer to the Intel ® 865G//865GV865PE/865P Chipset Platform Design Guide .<br><br> 1.3 Intel ® 865G Chipset System Overview Figure 1 shows an example block diagram of an 865G chipset-based platform. The 865G chipset is designed for use in a desktop system based on a Pentium 4 processor with 512-KB L2 cache on 0.13 micron process and the Pentium 4 processor on 90 nm process. The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol.<br><br> The GMCH provides the processor interface, system memory interface, CSA interface, AGP interface, hub interface, and additional interfaces. The GMCH contains and integrated graphics device. The 865G chipset platform supports either an integrated graphics device (IGD) or an external graphics device on AGP.<br><br> The IGD has 3D, 2D, and video capabilities. The IGD also has two multiplexed Intel DVO ports to support DVO devices. The GMCH 9s AGP interface supports 1X/4X/8X AGP data transfers and 4X/8X AGP Fast Writes, as defined in the Accelerated Graphics Port Interface Specification, Revision 3.0 .<br><br> The GMCH provides a Communications Streaming Architecture (CSA) Interface that connects the GMCH to a Gigabit Ethernet (GbE) controller. The 865G chipset platform supports 4 GB of system memory and has a maximum bandwidth of 6.4 GB/s using DDR400 in dual-channel mode. The 82801EB ICH5 integrates an Ultra ATA 100 controller, two Serial ATA host controllers, one EHCI host controller, and four UHCI host controllers supporting eight external USB 2.0 ports, LPC interface controller, flash BIOS interface controller, PCI interface controller, AC 997 digital controller, integrated LAN controller, an ASF controller and a hub interface for communication with the GMCH.<br><br> The ICH5 component provides the data buffering and interface arbitration required to ensure that system interfaces operate efficiently and provide the bandwidth necessary to enable the system to obtain peak performance. The 82801ER ICH5R elevates Serial ATA storage performance to the next level with Intel ® RAID Technology. The ACPI compliant ICH5 platform can support the Full-on, Stop Grant, Suspend to RAM, Suspend to Disk, and Soft-Off power management states.<br><br> Through the use of the integrated LAN functions, the ICH5 also supports Alert Standard Format for remote management. Intel ® PC SDRAM Specification http://developer.intel.com/ technology/memory/pcsdram/ spec/index.htm Accelerated Graphics Port Interface Specification, Revision 2.0 http://www.intel.com/ technology/agp/agp_index.htm Digital Visual Interface (DVI) Specification, Revision 1.0 http://www.ddwg.org/ downloads.html Document Document Number/ Location Intel ® 82865G/82865GV GMCH Datasheet 19 Introduction Figure 1. Intel ® 865G Chipset System Block Diagram Processor Intel ® 82865G GMCH DDR DDR DDR DDR Channel A 2.1 GB/s up to 3.2 GB/s 400/533/800 MHz FSB AGP 8x/ 2 multiplexed DVO ports 2.1 GB/s Intel ® 82801EB ICH5 or Intel ® 82801ER ICH5R 266 MB/s HI 1.5 USB 2.0 8 ports, 480 Mb/s GPIO 2 Serial ATA Ports 150 MB/s 2 ATA 100 Ports SIO Flash BIOS PCI Bus Six PCI Masters 2.1 GB/s up to 3.2 GB/s Channel B CSA Interface Gigabit Ethernet 266 MB/s AC '97 3 CODEC support LPC Interface Power Management Clock Generation System Management (TCO) LAN Connect/ASF SMBus 2.0/I 2 C Intel ® 865G Chipset System Memory VGA 20 Intel ® 82865G/82865GV GMCH Datasheet Introduction 1.4 Intel ® 82865G GMCH Overview The GMCH provides the host bridge interfaces and has an integrated graphics device with display interfaces.<br><br> The GMCH contains advanced desktop power management logic. The GMCH 9s role in a system is to provide high performance integrated graphics and manage the flow of information between its six interfaces: the processor front side bus (FSB), the memory attached to the SDRAM controller, the AGP 3.0 port, the hub interface, CSA interface, and display interfaces. This includes arbitrating between the six interfaces when each initiates an operation.<br><br> While doing so, the GMCH supports data coherency via snooping and performs address translation for accesses to the AGP aperture memory. To increase system performance, the GMCH incorporates several queues and a write cache. 1.4.1 Host Interface The GMCH supports a single, Pentium 4 processor with 512-KB L2 cache on 0.13 micron process.<br><br> The processor interface supports the Pentium 4 processor subset of the Extended Mode of the Scalable Bus Protocol. The GMCH supports FSB frequencies of 400/533/800 MHz (100 MHz, 133 MHz, and 200 MHz HCLK, respectively) using a scalable FSB VCC_CPU. It supports 32-bit host addressing, decoding up to 4 GB of the processor 9s memory address space.<br><br> Host-initiated I/O cycles are decoded to AGP/PCI_B, Hub Interface, or the GMCH configuration space. Host-initiated memory cycles are decoded to AGP/PCI_B, Hub Interface or system memory. All memory accesses from the host interface that hit the graphics aperture are translated using an AGP address translation table.<br><br> AGP/PCI_B device accesses to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated from AGP/PCI_B using PCI semantics and from hub interface to system SDRAM will be snooped on the host bus. 1.4.2 System Memory Interface The GMCH integrates a system memory DDR controller with two, 64-bit wide interfaces (up to two channels of DDR).<br><br> Only Double Data Rate (DDR) SDRAM memory is supported; thus, the buffers support only SSTL_2 signal interfaces. The memory controller interface is fully configurable through a set of control registers. System Memory Interface " Supports one or two 64-bit wide DDR data channels " Available bandwidth up to 3.2 GB/s (DDR400) for single-channel mode and 6.4 GB/s (DDR400) in dual-channel mode.<br><br> " Support for non ECC DIMMs " Supports 128-Mb, 256-Mb, 512-Mb DDR technologies " Supports only x8, x16, DDR devices with 4-banks " Registered DIMMs not supported " Supports opportunistic refresh " Up to 16 simultaneously open pages (four per row, four rows maximum) " SPD (Serial Presence Detect) scheme for DIMM detection support " Suspend-to-RAM support using CKE " Supports configurations defined in the JEDEC DDR1 DIMM specification only Intel ® 82865G/82865GV GMCH Datasheet 21 Introduction Single-Channel DDR Configuration " Up to 4.0 GB of DDR " Supports up to four DDR DIMMs (2 DIMMs per channel), single-sided and/or double-sided " Supports DDR266, DDR333, and DDR400 unregistered non-ECC DIMMs " Supports up to 32 simultaneous open pages " Does not support mixed-mode / uneven double-sided DDR DIMMs Dual-Channel DDR Configuration - Lockstep " Up to 4.0 GB of DDR " Supports up to four DDR DIMMs, single-sided and/or double-sided " DIMMS must be populated in identical pairs for dual-channel operation " Supports 16 simultaneous open pages (four per row) " Supports DDR266, DDR333, and DDR400 unregistered non-ECC DIMMs 1.4.3 Hub Interface Communication between the GMCH and the ICH5 occurs over the hub interface. The GMCH supports HI 1.5 that uses HI 1.0 protocol with HI 2.0 electrical characteristics. The hub interface runs at 266 MT/s (with 66 MHz base clock) and uses 1.5 V signaling.<br><br> Acceses between hub interface and AGP/PCI_B are limited to hub interface-originated memory writes to AGP. 1.4.4 Communications Streaming Architecture (CSA) Interface The CSA interface connects the GMCH with a Gigabit Ethernet (GbE) controller. The GMCH supports HI 1.5 over the interface that uses HI 1.0 protocol with HI 2.0 electrical characteristics.<br><br> The CSA interface runs at 266 MT/s (with 66 MHz base clock) and uses 1.5 V signaling. 1.4.5 Multiplexed AGP and Intel ® DVO Interface The GMCH multiplexes an AGP interface with two Intel ® DVOs ports. AGP Interface A single AGP or PCI 66 component or connector (not both) is supported by the GMCH 9s AGP interface.<br><br> Support for AGP 3.0 includes 0.8 V and 1.5 V AGP electrical characteristics. Support for a single PCI-66 device is limited to the subset supported by the AGP 2.0 specification. An external graphics accelerator is not a requirement due to the GMCH 9s integrated graphics capabilities.<br><br> The BIOS will disable the IGD if an external AGP device is detected. The AGP PCI_B buffers operate only in the 1.5 V mode and support the AGP 1.5 V connector. The AGP/PCI_B interface supports up to 8X AGP signaling and up to 8X Fast Writes.<br><br> AGP semantic cycles to system DDR are not snooped on the host bus. PCI semantic cycles to system DDR are snooped on the host bus. The GMCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both simultaneously.<br><br> Either the PIPE# or the SBA[7:0] mechanism must be selected during system initialization. The GMCH contains a 32 deep AGP request queue. High- priority accesses are supported.<br><br> 22 Intel ® 82865G/82865GV GMCH Datasheet Introduction DVO Multiplexed Interface The GMCH supports two multiplexed DVO ports that each drive pixel clocks up to 165 MHz. The DVO ports can each support a single-channel DVO device. If both ports are active in single- channel mode, they will have identical display timings and data.<br><br> Alternatively, the DVO ports can be combined to support dual-channel devices that have higher resolutions and refresh rates. The GMCH can make use of these digital display channels via an AGP Digital Display (ADD) card. 1.4.6 Graphics Overview The GMCH provides an integrated graphics accelerator delivering cost competitive 3D, 2D, and video capabilities.<br><br> The GMCH contains an extensive set of instructions for 3D operations, BLT and Stretch BLT operations, motion compensation, overlay, and display control. The GMCH 9s video engines support video conferencing and other video applications. The GMCH does not support a dedicated local graphics memory interface; it may only be used in a UMA configuration.<br><br> The GMCH also has the capability to support external graphics accelerators via AGP; The IGD cannot work concurrently with an external AGP graphics device. High bandwidth access to data is provided through the system memory port. The GMCH can access local and AGP graphics data located in system memory to 4.2 GB/s (DDR266), 5.4 GB/s (DDR333), or 6.4 GB/s (DDR400) depending on whether single/dual channel memory configuration.<br><br> The GMCH also provides 2D hardware acceleration for block-level transfers of data (BLTs). The BLT engine provides the ability to copy a source block of data to a destination and perform raster operations (e.g., ROP1, ROP2, and ROP3) on the data using a pattern, and/or another destination. Performing these common tasks in hardware reduces processor load, and thus improves performance.<br><br> The internal graphics device incorporated in the GMCH is incapable of operating in parallel with an attached AGP device. Intel ® 82865G/82865GV GMCH Datasheet 23 Introduction The graphics features on the GMCH include the following: " Core Frequency of 266 MHz " VGA/UMA Support " High Performance 3D Setup and Render Engine 4 Setup matching processor geometry delivery rates 4 Triangle Lists, Strips and Fans Support 4 Indexed Vertex and Flexible Vertex Formats 4 Vertex Cache 4 Pixel Accurate Fast Scissoring and Clipping Operation 4 Backface Culling Support 4 Supports D3D and OGL Pixelization Rules 4 Anti-aliased Lines Support 4 Sprite Points Support " High-Quality/Performance Texture Engine 4 Per Pixel Perspective Corrected Texture Mapping 4 Single Pass Quad Texture Compositing 4 Enhanced Texture Blending Functions 4 12 Level of Detail MIP Map Sizes from 1x1 to 2Kx2K 4 All texture formats including 32-bit RGBA and 8-bit palettes 4 Alpha and Luminance Maps 4 Texture Color-keying/ChromaKeying 4 Bilinear, Trilinear and Anisotropic MIP-Mapped Filtering 4 Cubic Environment Reflection Mapping 4 Embossed and DOT3 Bump-Mapping 4 DXTn Texture Decompression 4 FXT1 Texture Compression 4 Non-power of 2 Texture 4 Render to Texture " 2D Graphics 4 Optimized 256-bit BLT Engine 4 Alpha Stretch Blitter 4 Anti-aliased Lines 4 32-bit Alpha Blended Cursor 4 Color Space Conversion 4 Programmable 3-Color Transparent Cursor 4 8-, 16- and 32-bit Color 4 ROP Support " 3D Graphics Rendering Enhancements 4 Flat and Gouraud Shading 4 Color Alpha Blending For Transparency 4 Vertex and Programmable Pixel Fog and Atmospheric Effects 4 Color Specular Lighting 4 Z Bias Support 4 Dithering 4 Line and Full-scene Anti-Aliasied 4 16- and 24-bit Z Buffering 4 16- and 24-bit W Buffering 4 8-bit Stencil Buffering 4 Double and Triple Render Buffer Support 4 16- and 32-bit Color 4 Destination Alpha 4 Vertex Cache 4 Maximum 3D Resolution Supported: 1600x1200x32 @ 85Hz 4 Fast Clear Support " Video DVD/PC-VCR 4 Hardware Motion Compensation for MPEG2 4 Dynamic Bob and Weave Support for Video Streams 4 Synclock Display and TV-out to video source 4 Source Resolution up to 1280x720 with 3-vertical taps and 1920x1080 with 2-vertical taps 4 Software DVD At 30 fps, Full Screen 4 Supports 720x480 DVD Quality Encoding at low processor Utilization for PC-VCR or home movie recording and editing 4 Video Overlay 4 Single High Quality Scalable Overlay 4 Multiple Overlay Functionality provided via Stretch Blitter (PIP, Video Conferencing, etc.) 4 5-tap Horizontal, 3-tap Vertical Filtered Scaling 4 Independent Gamma Correction 4 Independent Brightness/Contrast/Saturation 4 Independent Tint/Hue Support 4 Destination Color-keying 4 Source ChromaKeying 4 Maximum Source Resolution: 720x480x32 4 Maximum Overlay Display Resolution: 2048x1536x32 " Video Mixer Render S

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